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Hybrid Single Electron Transistor Based Low Power Consuming Odd Parity Generator and Parity Checker Circuit in 22 nm Technology

  • Sudipta Mukherjee
  • Anindya Jana
  • Subir Kumar Sarkar
Conference paper
Part of the Smart Innovation, Systems and Technologies book series (SIST, volume 31)

Abstract

Co-fabrication between single electron transistor (SET) and CMOS technology has already proved to be feasible in production of future low power ultra dense circuitry. Mutual integration between this two can thus be efficient in computing applications. Here, an odd parity generator and parity checker circuit is build up with hybridization of SET-CMOS technology using Mahapatra-Ionescu-Banerjee (MIB model) and BSIM 4.6.1 model. Power consumption and PDP are also calculated and compared numerically and graphically with the conventional CMOS technology.

Keywords

MIB BSIM4.6.1 Parity generator Parity checker Hybrid SET-CMOS 

Notes

Acknowledgments

Subir Kumar Sarkar thankfully acknowledges the financial support obtained in the form of fellowship from UGC UPE PHASE-II, “Nano Science and Technology”.

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Copyright information

© Springer India 2015

Authors and Affiliations

  • Sudipta Mukherjee
    • 1
  • Anindya Jana
    • 1
  • Subir Kumar Sarkar
    • 1
  1. 1.Department of Electronics and Telecommunication EngineeringJadavpur UniversityKolkataIndia

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