Design Challenges in Subthreshold Interconnect Circuits

Abstract

As technology advances to giga-scale integration level, global interconnect resource becomes increasingly valuable in a VLSI chip. This is due to the exponential growth of the total number of interconnects/wires as the feature size of MOS transistors decreases in scaled deep submicron CMOS technologies. Interconnect length, however, has not scaled down with feature size and remains long relative to other on-chip geometries. Interconnects are metal or polysilicon wires which connect billions of active devices to carry signals within a VLSI chip. There are a number of such wires in the whole chip. Of these, the length of long interconnects in large chips is of the order of 10 mm.