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A 4-bit 9 KS/s Distortionless Successive Approximation ADC in 180-nm CMOS Technology

  • P. Dipu
  • B. Saidulu
  • K. Aravind
  • Johny S. Raj
  • K. Sivasankaran
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 324)

Abstract

In recent years, analog-to-digital converters are the crucial part of many applications. In this paper, we proposed a 1.8 V capacitor-array-based successive approximation ADC. This SAR ADC uses bootstrapped switch to decrease distortion, and comparison is done using a pre-amplifier preceding a latched comparator. A 4-bit SAR ADC with high resolution was designed in 180-nm CMOS process. This paper aims at describing the design of a discrete-component, successive approximation register analog-to-digital converter (SAR ADC). The performance evaluation was done using Cadence ADE tool.

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Copyright information

© Springer India 2015

Authors and Affiliations

  • P. Dipu
    • 1
  • B. Saidulu
    • 1
  • K. Aravind
    • 1
  • Johny S. Raj
    • 1
  • K. Sivasankaran
    • 1
  1. 1.School of Electronics Engineering (SENSE)VIT UniversityVelloreIndia

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