Design of Quantum Cost and Delay-Optimized Reversible Wallace Tree Multiplier Using Compressors

  • A. N. Nagamani
  • Vinod Kumar Agrawal
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 324)


Compressors play a specific role in realizing high-speed arithmetic circuits in particular multipliers. The increase in the demand of fast multiplication has attracted many researchers to design higher order compressors which enhance the speed of computation by reducing the critical path delay of the processing unit. In this paper, quantum cost and delay-optimized compressors are proposed. The compressors are designed using existing reversible gates such as Feynman, Fredkin, and Peres gates (PG). Using these optimized compressors, 8 × 8 Wallace multiplier is designed and the performance parameters are compared with the existing designs in the literature. It is evident from the results that this design exhibits better performance parameters and lesser delay and hence it is faster compared to existing designs in the literature. Thus, this design is suitable for high-speed arithmetic circuits such as FFTs, IFTs in modern DSP design.


Compressors Fast arithmetic Multipliers Nanotechnology Reversible logic 


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Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.Department of Electronic and CommunicationPES Institute of TechnologyBangaloreIndia
  2. 2.Department of Information Science and EngineeringPES Institute of TechnologyBangaloreIndia

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