Design of Quantum Cost and Delay-Optimized Reversible Wallace Tree Multiplier Using Compressors

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 324)

Abstract

Compressors play a specific role in realizing high-speed arithmetic circuits in particular multipliers. The increase in the demand of fast multiplication has attracted many researchers to design higher order compressors which enhance the speed of computation by reducing the critical path delay of the processing unit. In this paper, quantum cost and delay-optimized compressors are proposed. The compressors are designed using existing reversible gates such as Feynman, Fredkin, and Peres gates (PG). Using these optimized compressors, 8 × 8 Wallace multiplier is designed and the performance parameters are compared with the existing designs in the literature. It is evident from the results that this design exhibits better performance parameters and lesser delay and hence it is faster compared to existing designs in the literature. Thus, this design is suitable for high-speed arithmetic circuits such as FFTs, IFTs in modern DSP design.

Keywords

Compressors Fast arithmetic Multipliers Nanotechnology Reversible logic 

References

  1. 1.
    R. Landauer, Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 3, 183–191 (1961)CrossRefMathSciNetGoogle Scholar
  2. 2.
    C.H. Bennett, Logical reversibility of computation. IBM J. Res. Dev. (1973)525–532Google Scholar
  3. 3.
    V.G. Oklobdzija, D. Villeger, S.S Liu, A method for speed optimized partial product reduction and generation of fast parallel multipliers using and algorithmic approach. IEEE Trans. Comput. 45(3) (1996)Google Scholar
  4. 4.
    P. Stelling, C. Martel, V.K. Oklobdzija, R. Ravi, Optimal circuits for parallel multipliers. IEEE Trans. Comput. 47(3), 273–285 (1998)CrossRefMathSciNetGoogle Scholar
  5. 5.
    V. Oklobdzija, High-speed VLSI arithmetic units: adders and multipliers, in Design of High-Performance Microprocessor Circuits (2000)Google Scholar
  6. 6.
    H.T. Bui, A.K. Al-Sheraidah, Wang, Y, Design and analysis of 10-transistor full adders using novel XORXNOR gates in Proceedings International Conference Signal Processing 2000 (2000)Google Scholar
  7. 7.
    H. Thapliyal, M.B. Srinivas, Novel reversible ‘TSG’ gate and its application for designing components of primitive/reversible quantum ALU, in Proceedings of 5th IEEE International Conference on Information, Communications and Signal Processing (2005) 1425–1429Google Scholar
  8. 8.
    E. Knil, R. Laflamme, G.J. Milburn, A scheme for efficient quantum computation with linear optics. Nature 46–52 (2001)Google Scholar
  9. 9.
    M. Nielsen, I. Chaung, in Quantum Computation and Quantum Information (Cambridge University Press 2000)Google Scholar
  10. 10.
    G. Schrom, in Ultra Low Power CMOS Technology. Ph.D. Thesis, Technischen Universitat Wien (1998)Google Scholar
  11. 11.
    H. Thapliyal, H.V. Jayashree, A.N. Nagamani, H.R. Arabnia, Progress in reversible processor design: a novel methodology for reversible carry look-ahead adder. Trans. Comput. Sci. XVII. 7420, 73–97 (2012)CrossRefGoogle Scholar
  12. 12.
    R. Feynman, Quantum Mechanical Computers. Optics News. 11, 11–20 (1985)CrossRefGoogle Scholar
  13. 13.
    E. Fredkin, T. Toffoli, Conservative logic. Int. J. Theory Phys. 21 219–253 (1982)Google Scholar
  14. 14.
    A. Peres, Reversible logic and quantum computers. Phys. Rev. A, Gen. Phys. 32(6) 3266–3276 (1985)Google Scholar
  15. 15.
    P. Gopineedi, H. Thapliyal, M.B. Srinivas, H.R. Arabnia, in Novel and efficient 4:2 and 5:2 compressors with minimum number of transistors designed for low-power operations in Proceedings of the 2006 International Conference on Embedded Systems and Applications (ESA’06) 017(5)160–166 (2006)Google Scholar
  16. 16.
    K. Prasad, K.K. Parhi, Low-power 4-2 and 5-2 compressors, in Proceedings of the 35th Asilomar Conference on Signals, Systems and ComputersI 129–133 (2001)Google Scholar
  17. 17.
    K. Ohsang, N. Kevin, E. Earl, Jr Swartzlander, A 16-Bit by 16-Bit MAC design using fast 5:3 compressor cells. J. VLSI Sig. Proc. 31 77–89 (2002)Google Scholar
  18. 18.
    R. Mahnoush, K. Omid, P.M. Amir, J.J. Somaye, N. Keivan, A new design for 7:2 compressors, in Proceedings. IEEE/ACS International Conference on communication, Networking and Broadcasting; computing and Processing (Hardware/Software) (2007)Google Scholar
  19. 19.
    V. Sreehari, M.K. Kirthi, A. Lingamneni, R.P. Sreekanth, M.B. Srinivas, Novel architectures for high-speed and low-power 3-2, 4-2 and 5-2 compressors, in 20th IEEE International Conference on VLSI Design (VLSID’07) (2007)Google Scholar
  20. 20.
    C.H. Chang, J.M. Gu, M. Zhang, Ultra low voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits. IEEE Trans. Circ. Syst.-I: Reg. Papers 51(10), 1985–1997 (2004)CrossRefGoogle Scholar
  21. 21.
    J. Yingtao, A novel multiplexer-based low-power full adder. IEEE Trans. Circ. Syst. II. Exp. Briefs 51(7) (2004)Google Scholar
  22. 22.
    P.J. Song, G.D. Micheli, Circuit and architecture tradeoffs for high-speed multiplication. IEEE J. Solid-State Circ. 26, 1184–1198 (1991)CrossRefGoogle Scholar
  23. 23.
    V.J. Oklobdzija, D. Villeger, S.S. Liu, A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Trans. Comput. 45, 294–305 (1996)CrossRefMATHGoogle Scholar
  24. 24.
    C.S. Wallace, A suggestion for a fast multiplier. IEEE Trans. Elec. Comput. 14–17 (1964)Google Scholar
  25. 25.
    D. Krishnaveni, M. Geetha Priya, K. Baskaran, Design of an efficient reversible 8 × 8 wallace tree multiplier. World Appl. Sci. J. 20(8), 1159–1165 (2012)Google Scholar
  26. 26.
    J. Donald, N.K. Jha, Reversible logic synthesis with Fredkin and Peres gates. ACM J. Emerg. Technol. Comput. Syst. 4 (2008)Google Scholar
  27. 27.
    P.W. Shor, Algorithms for quantum computation: discrete logarithms and factoring, in IEEE Computer Society Press. 124–134 (1994)Google Scholar
  28. 28.
    P.W. Shor, Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer. quant-ph/9508027. 2 (1997)Google Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.Department of Electronic and CommunicationPES Institute of TechnologyBangaloreIndia
  2. 2.Department of Information Science and EngineeringPES Institute of TechnologyBangaloreIndia

Personalised recommendations