Abstract
One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated because the usable voltage ranges are decreasing with every new integration step. The continued progress in increasing performance, speed, reliability, and the simultaneous reduction in size and cost of integrated circuits (LSI and VLSI) has resulted in a strong interest in implementation of the phase-locked loop (PLL) in the digital domain. In this chapter an overview of the Digital Phase-Locked-Loop (DPLL) system architecture is presented. An introduction to the operation is given, considering each of the DPLL components individually. The discrete time mathematical models of the various components of DPLL are discussed. Finally, the chapter ends with notes on classification of DPLL based on phase detection techniques, operational principles of various types of phase detector are also discussed.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Natali FD (1968) Accurate digital detection of angle modulated signals. In: 1968 EASCON Record, October 1968, pp 407–412
Holmes JK (1972) Performance of a fist-order transition sampling digital phase-locked loop using random-walk models. IEEE Commun Technol COM-20:119–131
Tegnelia CR (1972) A simple second-order digital phase-locked loop. In: Proceedings of the international telemetering conference, October 1972, vol VIII, pp 108–118
Holmes JK, Tegnelia CR (1974) A second-order all digital phase locked loop. IEEE Trans Commun Technol COM-22:62–68
Larimore WE (1968) Synthesis of digital phase-locked loop. In: EASCON Record, October 1968, pp 14–20
Greco J, Garodnick J, Schilling DL (1972) An all digital phase locked loop for FM demodulation. In: Roc. Znt, Con Communications, June 1972
Greco et al (1972) An all digital phase locked loop. In: Roc. Znt. Telemetering Conf., October 1972, vol VIII, pp 119–123
Greco J, Schilling DL (1973) An all digital phase locked loop for FM demodulation. In: Roc. Znr. Conf. Communications, June 1973, pp 43:37 43:41
Garodnick J, Grew J, Schilling DL (1974) Response of an all digital phase-locked loop. IEEE Trans Commun Technol COM-22:751–764
Haykin S (1994) Communication systems. Wiley, New York
Rabiner LR, Gold B (1975) Theory and application of digital signal processing. Prentice-Hall, Englewood Cliffs
Proakis JG, Manolakis DG (1968) Introduction to digital signal processing. Macmillan Publishing Company, London
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2015 Springer India
About this chapter
Cite this chapter
Purkayastha, B.B., Sarma, K.K. (2015). Digital Phase-Locked Loop. In: A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel. Signals and Communication Technology. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2041-1_5
Download citation
DOI: https://doi.org/10.1007/978-81-322-2041-1_5
Published:
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-2040-4
Online ISBN: 978-81-322-2041-1
eBook Packages: EngineeringEngineering (R0)