Efficient VLSI Implementation of CORDIC-Based Direct Digital Synthesizer
This paper presents efficient VLSI implementation of a direct digital synthesizer (DDS). Coordinate rotation digital computer (CORDIC) architecture is used in realizing the phase-to-amplitude converter (PAC) block in the proposed design. The proposed synthesizer has a frequency control word (FCW) that can select up to three different values for the phase increment. The proposed design is realized in Xilinx Virtex II Pro FPGA development board and is tested for its functionality using ChipScope Pro. The proposed design is mapped on to several families of Xilinx FPGAs for comparing the performance. Proposed synthesizer is also implemented using ASIC design flow. In the reported design, quadrature outputs can be obtained simultaneously.
KeywordsCORDIC Direct digital synthesizer FPGA Xilinx ASIC
This work is done as a part of master’s thesis of the first author. Authors thank the VLSI Laboratory of NIT Rourkela for providing with the necessary tools and kits.
- 1.Volder, J.E.: The CORDIC trigonometric computing technique. IRE Trans. Electron. Comput. EC–8, 330–334 (1959)Google Scholar
- 2.Walther, J.S.: A unified algorithm for elementary functions. Joint Spring Comput. Conf. 38, 379–385 (1971)Google Scholar
- 3.Bramble, A.L.: Direct digital frequency synthesis. In: 35th Annual Frequency Control Symposium, pp. 406–414 (1981)Google Scholar
- 10.Sung, T.-Y., Kyo, L.-T., Hsin, H.-C.: Low-power and high-SFDR direct digital frequency synthesizer based on hybrid CORDIC algorithm. In: International Symposium on Circuits and Systems, pp. 249–252 (2009)Google Scholar
- 11.Prasad, N., Swain, A.K., Mahapatra, K.K.: FPGA implementation of pipelined CORDIC based quadrature direct digital synthesizer with improved SFDR. In: 2013 International Conference on Circuits, Power, and Computing Technologies, pp. 756–760 (2013)Google Scholar