The Impact of Gate Underlap on Analog and RF Performance of Hetero-Junction FET

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 308)


Due to enhanced carrier mobility, InP/InGaAs heterostructure double gate MOSFET evinced himself as an attractive candidate for applications in high performance digital logic circuits. In this paper, our aim was to analyze the impact of gate underlap on analog and RF performance of InP/InGaAs hetero-junction FET using TCAD device simulator. The analog and RF parameters of HFET such as drain resistance (R o), transconductance (g m), and unity-gain cutoff frequency (f T) are studied for varying underlap length raging from 2 to 9 nm. It is shown that the analog and RF performance of hetero-junction FET is severely affected by amount of underlap and this effect can be moderated by an optimal underlap, which yields a trade-off between the analog and RF performance.


Hetero-junction FET Gate underlap Analog/RF performance Unity-gain cutoff frequency Transconductance Drain resistance 


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Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.ECE DepartmentKalyani Government Engineering CollegeKalyaniIndia

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