Advertisement

The Impact of Gate Underlap on Analog and RF Performance of Hetero-Junction FET

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 308)

Abstract

Due to enhanced carrier mobility, InP/InGaAs heterostructure double gate MOSFET evinced himself as an attractive candidate for applications in high performance digital logic circuits. In this paper, our aim was to analyze the impact of gate underlap on analog and RF performance of InP/InGaAs hetero-junction FET using TCAD device simulator. The analog and RF parameters of HFET such as drain resistance (R o), transconductance (g m), and unity-gain cutoff frequency (f T) are studied for varying underlap length raging from 2 to 9 nm. It is shown that the analog and RF performance of hetero-junction FET is severely affected by amount of underlap and this effect can be moderated by an optimal underlap, which yields a trade-off between the analog and RF performance.

Keywords

Hetero-junction FET Gate underlap Analog/RF performance Unity-gain cutoff frequency Transconductance Drain resistance 

References

  1. 1.
    Woerlee, P.H., Knitel, M.J., van Langevelde, R., Klaassen, D.B.M., Tiemeijer, L.F., Scholten, A.J., Zegers-van Duijnhoven, A.T.A.: RF-CMOS performance trends. IEEE Trans Electron Devices 48(8), 1776, 1782 (2001)Google Scholar
  2. 2.
    Pardeshi, H., Raj, G., Pati, S.K., Mohankumar, N., Sarkar, C.K.: Comparative assessment of III–V heterostructure and silicon underlap double gate MOSFETs. Semiconductors 46(10), 1299–1303 (2012)CrossRefGoogle Scholar
  3. 3.
    Chau, R., Datta, S., Majumdar, A.: Opportunities and challenges of III–V nanoelectronics for future high-speed, low-power logic applications. In: Compound Semiconductor Integrated Circuit Symposium, CSIC’05, p. 4, 30 Oct–2 Nov 2005. IEEEGoogle Scholar
  4. 4.
    Oktyabrsky, S., Ye, P.: Fundamentals of III–V Semiconductor MOSFETs. Springer, Berlin (2010)Google Scholar
  5. 5.
    Nainani, A., Yuan, Z., Krishnamohan, T., Saraswat, K.: Optimal design of III–V heterostructure MOSFETs. In: 2010 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 103, 106, 6–8 Sept 2010Google Scholar
  6. 6.
    Bansal, A., Paul, B.C., Roy, K.: Modeling and optimization of fringe capacitance of nanoscale DGMOS devices. IEEE Trans Electron Devices 52(2), 256, 262 (2005)Google Scholar
  7. 7.
    Bansal, A., Roy, K.: Analytical subthreshold potential distribution model for gate underlap double-gate MOS transistors. IEEE Trans. Electron Devices 54(7), 1793, 1798 (2007)Google Scholar
  8. 8.
    Trivedi, V., Fossum, J.G., Chowdhury, M.M.: NanoscaleFinFETs with gate-source/drain underlap. IEEE Trans Electron Devices 52(1), 56, 62 (2005)Google Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.ECE DepartmentKalyani Government Engineering CollegeKalyaniIndia

Personalised recommendations