A Novel Low-Power Domino Logic Technique Providing Static Output in Evaluation Phase for High Frequency Changing Inputs

  • Sumit Sharma
  • Kamal Kant Kashyap
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 308)


Domino logic is widely used for high switching speed and high-performance circuits. Domino logic consists of an inverter used between two stages of dynamic logic. Robustness of domino logic degrades with scaling down as leakage power increases. This paper presents a new proposed domino logic circuit with improved speed. Present work proposed domino logic scheme which gives static output also in evaluation phase with high frequency inputs. Conventional domino styles do not provide static output with changing inputs during evaluation phase. This proposed circuit is designed by making use of current mirror circuit and modified keeper circuitry. The proposed circuit has low power-delay product as compared to conventional domino logic styles. All the circuits have been simulated in cadence virtuoso 180 nm technology. According to simulation results obtained, the circuit shows more than 50 % better performance as compared to conventional domino styles.


Domino logic Dynamic gates Evaluation phase Pre-charge phase Static gates Robustness 


  1. 1.
    Rabaey, M., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits, 2nd edn, pp. 269–274. Prentice Hall, Englewood Cliffs (2002)Google Scholar
  2. 2.
    Neil, H.E., David, H.: Principle of CMOS VLSI design: a system perpective, 3rd edn. Addison-Wesley, Reading (2004)Google Scholar
  3. 3.
    Sung, R.J.-H., Elliott, D.G.: Clock-logic domino circuits for high-speed and energy-efficient microprocessor pipelines. IEEE Trans. Circuits Syst. II Express Briefs 54(5), 460 (2007)CrossRefGoogle Scholar
  4. 4.
    Das, K.K. et al.: Low-leakage integrated circuits and dynamic logic circuits. U.S. Patent 6933744 (2005)Google Scholar
  5. 5.
    Moradi, F., Vu Cao, T., Vatajelu, E., Peiravi, A., Mahmoodi, H., Wisland, D.: Domino logic designs for high-performance and leakage-tolerant applications. Int. VLSI J. 46, 247–254 (2013)CrossRefGoogle Scholar
  6. 6.
    Anis, M.H., Allam, M.W., Elmasry, M.I.: Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 10, 71–78 (2002)CrossRefGoogle Scholar
  7. 7.
    Oklobdzija, V.G., Montoye, R.K.: Design-performance tradeoffs in CMOS-domino logic. IEEE J. Solid State Circuits 21(2), 304–306 (1986)CrossRefGoogle Scholar
  8. 8.
    Ding, L., Mazumder, P.: On circuit techniques to improve noise immunity of CMOS dynamic logic. IEEE Trans. Circ. Syst. 12, 910–925 (2004)Google Scholar
  9. 9.
    Gray, P.R., Hurst, P.J., Lewis, S.H., Meyer, R.G.: Analysis and Design of Analog Integrated Circuits. Wiley, New York (1984)Google Scholar
  10. 10.
    Kursun V, Friedman EG (2002) Low swing dual threshold voltage domino logic. In: Proceedings ACM/SIGDA Lakes Symposium on VLSI, pp. 47–52Google Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.School of VLSI Design and Embedded SystemsNIT KurukshetraKurukshetraIndia
  2. 2.ECE DepartmentNIT KurukshetraKurukshetraIndia

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