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Leakage Power Minimization

  • Ajit PalEmail author
Chapter

Abstract

This chapter is concerned with leakage power minimization techniques. As leakage power minimization techniques exploit the threshold voltage to minimize leakage power, the dependence of delay and leakage power on threshold voltage is discussed first. Various techniques for the fabrication of multiple threshold voltages are briefly discussed. A standby leakage power minimization technique using the variable-threshold-voltage complementary metal–oxide–semiconductor (VTCMOS) approach is presented. How standby leakage power can be minimized by using the stack effect is explained. Run-time leakage power minimization by using the multiple-threshold-voltage metal–oxide–semiconductor (MTCMOS) approach is elaborated. One of the most popular techniques for leakage power reduction is power gating, which also involves the use of multiple-threshold-voltage transistors. Various issues related to the power-gating approach are discussed. The power management approach used to reduce leakage power dissipation and how it can be combined with the dynamic voltage scaling approach are explained. Both delay-constrained and energy-constrained dual-V th approaches to minimize leakage power dissipation are presented. Finally, the dynamic V t scaling approach to minimize leakage power dissipation is highlighted.

Keywords

Multiple channel doping Multiple oxide thickness Multiple channel length Multiple body bias Transistor stacking Variable-threshold-voltage CMOS (VTCMOS) Multi-threshold-voltage CMOS (MTCMOS) Active mode Sleep mode Power gating Switch in cell Switching fabric Isolation cell Isolation strategy State retention State retention strategy Vth hopping Power-gating controller Power management DTCMOS Dual-Vt assignment 

References

  1. 1.
    Roy, K., Mukhopadhyay, S., Mahmooddi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, vol. 91, no. 2, pp. 305–327, February (2003)Google Scholar
  2. 2.
    Inukai, T., Hiramoto, T., Sakurai, T.: Variable Threshold Voltage CMOS (VTCMOS) in series connected circuits, ISPLED ’01, Huntington Beach, California, USA, pp. 201–206, August 6–7 (2001)Google Scholar
  3. 3.
    Kang, Sung Mo, Leblebici, Y. : CMOS digital integrated circuits-analysis and design, 3rd edn. Tata McGraw Hill, New Delhi (2003)Google Scholar
  4. 4.
    Johnson, M.C., Roy, K., Somaskhar, D.: A model for leakage control by transistor stacking, Technical Report TR-ECE 97-12, Purdue University (1997)Google Scholar
  5. 5.
    Gu, R.X., Elmasry, M.I.: Power dissipation analysis and optimization of deep submicron CMOS digital circuits, IEEE JSSC 31(5):707–713 (1996)Google Scholar
  6. 6.
    Yang, S., Wolf, W., Vijaykrishnan, N., Xie, Y., Wang, W.: Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits. Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05), Kolkata, January 3–7 (2005)Google Scholar
  7. 7.
    Mutoh, S., et al.: A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application, International Solid-State Circuits Conference (ISSCC), pp. 168–169, Feb. (1996)Google Scholar
  8. 8.
    Keating, M., Flynn, D., Aitken, R., Gibbons, R., Shi, K.: Low power methodology manual: for system-on-chip design, Springer (2007)Google Scholar
  9. 9.
    ACPI, Hewlett-Packard, Intel Corporation, Microsoft , Phoenix Technologies, Toshiba (2011-12-06). Advanced Configuration and Power Interface Specification (Revision 5.0)Google Scholar
  10. 10.
    Wei, L., Chen, Z., Roy, K., Johnson, M.C., Ye, Y., De, V.: Design and optimization of dual threshold circuits for low voltage low power applications, IEEE Trans. VLSI Syst. 17(1):16–24 (1999)CrossRefGoogle Scholar
  11. 11.
    Kim, Chris H., Roy, K.: Dynamic VTH scaling scheme for active leakage power reduction, Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE02), pp. 163–167 (2002)Google Scholar
  12. 12.
    Tripathi, N., Bhosle, A., Samanta, D., Pal, A.: Optimal assignment of high-V T for synthesizing dual-V T CMOS circuits, IEEE/ACM Proceedings of the 14th International Conference on VLSI Design, pp. 227–232, January (2001)Google Scholar
  13. 13.
    Samanta, D., Pal, A.: Optimal dual-V T assignment for low-voltage energy-constrained CMOS circuits, IEEE/ACM Proceedings of the 7th ASP-DAC and 15th International Conference on VLSI Design, pp. 193–198, January (2002)Google Scholar
  14. 14.
    Sundararajan, V., Parhi, K.K.: Low power synthesis of dual threshold voltage CMOS VLSI circuits, IEEE/ACM Proceedings of the International Symposium on Low Power Electronics Design (ISLPED), pp. 363–368, July (1999)Google Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.Computer Science and EngineeringIndian Institute of Technology KharagpurKharagpurIndia

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