Advertisement

Supply Voltage Scaling for Low Power

  • Ajit PalEmail author
Chapter

Abstract

This chapter focuses on supply voltage scaling which is the most effective way to reduce power dissipation. First, the challenges involved in supply voltage scaling for low power are highlighted. Then, the difference between constant-field and constant-voltage scaling are explained in the context of feature size scaling. The short-channel effects arising out of feature size scaling are also discussed. Architecture-level approaches for low power, using parallelism and pipelining are explored. Multi-core processor architecture as an approach for low power is explained. Voltage scaling techniques using high-level transformations are presented. The multilevel voltage scaling (MVS) approach is introduced and various challenges in MVS are discussed. The implementation of dynamic voltage and frequency scaling (DVFS) approach is presented. Then, a close-loop approach known as the adaptive voltage scaling (AVS) is implemented which monitors the performance at execution time to estimate the required supply voltage and accordingly voltage scaling is performed. Finally, subthreshold circuits are introduced that operate with a supply voltage less than the threshold voltage of the metal–oxide–semiconductor (MOS) transistors, resulting in a significant reduction of power dissipation at the cost of longer delay.

Keywords

Static voltage scaling Multilevel voltage scaling Dynamic voltage scaling Adaptive voltage scaling Feature size scaling Constant-field scaling Constant-voltage scaling Short-channel effects Parallelism for low power Pipelining for low power Multi-core for low power High-level transformations Voltage-scaling interfaces Level converters Converter placement Dynamic voltage scaling (DVS) Dynamic voltage and frequency scaling Workload prediction Adaptive voltage scaling 

References

  1. 1.
    Kang, S-M., Leblebici, Y.: CMOS Digital Integrated Circuits Analysis and Design, 3rd edn. Tata McGraw-Hill, Noida (2003)Google Scholar
  2. 2.
    Chandrakasan, A.P., Brodersen, R.W.: Low-Power Digital CMOS Design. Kluwer, Norwell (1995)CrossRefGoogle Scholar
  3. 3.
    Bellaouar, A., Elmasry, M.I.: Low-Power Digital VLSI Design. Kluwer, Norwell (1995)CrossRefGoogle Scholar
  4. 4.
    Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low-power CMOS digital design. IEEE J. Solid-State Circuits 27(4):473–484 (1992)CrossRefGoogle Scholar
  5. 5.
    Keating, M., Flynn, D., Aitken, R., Gibbons, A., Shi, K.: Low Power Methodology Manual: For System-on-Chip Design. Springer (2007)Google Scholar
  6. 6.
    Sinha, A., Chandrakasan, A.P.: Dynamic voltage scheduling using adaptive filtering of workload traces. In: Proceedings of 14th VLSI Design 2001 Conference, pp. 221–226, Jan 2001Google Scholar
  7. 7.
    Nakai, M., Akui, S., Seno, K., Meguro, T., Seki, T., Kondo, T., Hashiguchi, A., Kawahara, H., Kumano, K., Shimura, M.: Dynamic voltage and frequency management for a low-power embedded microprocessor. IEEE J. Solid-State Circuits 40(1):28–35 (2005)CrossRefGoogle Scholar
  8. 8.
    Vaddi, R., Dasgupta, S., Agarwal, R.P.: Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications, VLSI Design, Hindawi, vol. 2009, Article ID 283702, 14 pp. (2009)Google Scholar
  9. 9.
    Vaddi, R., Dasgupta, S., Agarwal, R.P.: Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS. IEEE Trans. Electron Devices 57(3):654–664 (2010)CrossRefGoogle Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.Computer Science and EngineeringIndian Institute of Technology KharagpurKharagpurIndia

Personalised recommendations