Online Testable Conservative Adder Design in Quantum Dot Cellular Automata

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 298)


Garbage count minimization and low power, lossless conservative full adder design and its online testing in Quantum dot Cellular Automata is prime research interest of this work. Parity preserving reversible logic design as well as conservative logic design is a lossless paradigm in Nanotechnology. Errors can be detected by means of parity in conservative logic design. We introduce a conservative logic gate to design full adder with zero garbage count. The proposed two conservative logic gate (PCLG) is universal in nature. A tester reversible logic gate (TRLG) is designed to perform online test of proposed conservative logic gate (PCLG). We demonstrate the most promising two PCLG and a TRLG to design full adder and to online test of PCLG respectively. We compared our PCLG with well-known Fredkin gate in terms of implementation of thirteen standard functions.


Parity preserving Conservative logic gate Reversible logic gate 5—input majority voter Online testing 


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Copyright information

© Springer India 2014

Authors and Affiliations

  1. 1.B. P. Poddar Institute of Management and TechnologyKolIndia
  2. 2.Department of Computer Science and EngineeringWest Bengal University of TechnologyKolkataIndia
  3. 3.School of PhysicsUniversity of Western AustraliaCrawley, PerthAustralia
  4. 4.Department of Engineering and Technological StudiesKalyani UniversityKalyaniIndia

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