Realization of Bi-Quinary Coded Decimal Adder in Quantum Dot Cellular Automata

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 298)

Abstract

Bi-quinary coded parallel adder design with Quantum Cellular Automata is presented in this brief contribution. The nano-electronic computer architecture using QCA technology is in infancy stage. It requires more advancement with new approaches. In this paper the design of parallel decimal adder is proposed using bi-quinary encoding techniques with algorithm. The circuits are implemented using QCA designer tool and analyzed using simulation result. The signal propagation delay, complexity, required area, hardware cost are calculated and compare with previously proposed decimal QCA adders.

Keywords

QCA basic 3 × 3 tile Decimal digit encoding Bi-quinary code Parallel decimal adder 

Notes

Acknowledgments

The authors are grateful to the University Grants Commission (UGC), India File No.: 41-631/2012(SR), under which this paper has been completed.

References

  1. 1.
    Lent CS, Taugaw PD, Porod W, Bernstein GH (1993) Quantum dot cellular automata. Nanotechnology 4:49–57CrossRefGoogle Scholar
  2. 2.
    Tougaw PD, Lent CS (1996) Dynamic behavior of quantum cellular automata. J Appl Phys 80(8):4722–4736CrossRefGoogle Scholar
  3. 3.
    Lent CS, Tougaw PD, Porod W (1993) Bistable saturation in coupled quantum dots for quantum cellular automata. Appl Phys Lett 62:7–14CrossRefGoogle Scholar
  4. 4.
    Gladshtein M (2011) Quantum-dot cellular automata serial decimal adder. IEEE Trans Nanotechnol 10(6): 1377–1382Google Scholar
  5. 5.
    Kharbash F, Chaudhry GM (2008) The design of quantum-dot cellular automata decimal adder. In: IEEE international multi-topic conference, INMIC 2008. IEEE (bcd adder)Google Scholar
  6. 6.
    Gladshtein MA (2010) The signal propagation delay reduction of the combinational adder of decimal digits encoded by the Johnson-Mobius code. Autom Control Comput Sci 44(2):103–109CrossRefGoogle Scholar
  7. 7.
    Gladshtein MA (2009) Algorithmic synthesis of a combinational adder of decimal digits encoded by the Johnson-Mobius code. Autom Control Comput Sci 43(5):233–240CrossRefGoogle Scholar
  8. 8.
    Das K, De D (2011) Characterisation, applicability and defect analysis for tiles nanostructure of quantum dot cellular automata. Mol Simul 37(03):210–225CrossRefGoogle Scholar
  9. 9.
    Das K, De D (2009) A Novel approach of And-Or-Inverter (AOI) gate design for QCA. In: Proceedings of IEEE conference CODEC-09 (14–16 Dec 2009), pp 1–4Google Scholar
  10. 10.
    Das K, De D (2011) A study on diverse nanostructure for implementing logic gate design for QCA. Int J Nanosci 10(1–2) (Feb and April 2011):263–269 (World Scientific)Google Scholar
  11. 11.
    Walus K et al (2004) QCA designer: a rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans Nanotechnol 3(1):26–31Google Scholar
  12. 12.
    Walus K et al (2002) ATIPS laboratory QCADesigner homepage. ATIPS laboratory, University of Calgary, Canada. http://www.atips.ca/projects/qcadesigner
  13. 13.
    Pudi V, Sridharan K (2012) Low complexity design of ripple carry and Brent–Kung adders in QCA. IEEE Trans Nanotechnol 11(1):105–119Google Scholar
  14. 14.
    Srivastava S, Sarkar S, Bhanja S (2009) Estimation of upper bound of power dissipation in QCA circuits. IEEE Trans Nanotechnol 8(1):116–127Google Scholar
  15. 15.
    Oklobdzija V (ed) (2002) The computer engineering handbook. CRC press, FloridaGoogle Scholar
  16. 16.
    Kashio T (1962) TOSHIO KASHIO. U.S. Patent No. 3,015,445. 2 Jan 1962Google Scholar

Copyright information

© Springer India 2014

Authors and Affiliations

  1. 1.B. P. Poddar Institute of Management and TechnologyKolkataIndia
  2. 2.Department of Computer Science and EngineeringWest Bengal University of TechnologySalt Lake City, KolkataIndia
  3. 3.Department of Engineering and Technological StudiesKalyani UniversityKalyaniIndia

Personalised recommendations