Abstract
In recent years, reversible logic has emerged as a major area of research due to its ability to reduce the power dissipation, which is the main requirement in the low-power digital circuit design. It has wide applications such as low-power CMOS design, nanotechnology, digital signal processing, communication, DNA computing, and optical computing. In this paper, two new 3 × 3 reversible gates are proposed and these are being used to realize the classical set of logic gates in the reversible domain. An important aspect of the two newly proposed reversible gates is that a novel optimized 1-bit comparator can be realized. The proposed reversible 1-bit comparator is better and optimized in terms of the number of reversible gates used, the number of transistor counts, and the number of garbage outputs. Also, a 4-bit comparator has been designed by cascading 1-bit comparators in series. Using this, a 32-bit reversible comparator has been proposed. Proposed circuits have been simulated using Modelsim.
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AnanthaLakshmi, A.V., Sudha, G.F. (2014). Transistor Representation of a Low-Power Reversible 32-Bit Comparator. In: Mohapatra, D.P., Patnaik, S. (eds) Intelligent Computing, Networking, and Informatics. Advances in Intelligent Systems and Computing, vol 243. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1665-0_7
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DOI: https://doi.org/10.1007/978-81-322-1665-0_7
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-1664-3
Online ISBN: 978-81-322-1665-0
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