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Simulation and Optimization of Channel Mobility in High-k/Metal Gate Nanoscale MOSFETs

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Book cover Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013)

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 258))

Abstract

The performance of submicron MOSFET with a thin conventional SiO2 gate dielectric degrades due to increasing gate leakage currents. High-k dielectric materials are used as alternate gate dielectric to overcome the problem. The introduction of high-k dielectric induces high interface charges which degrades both the mobility and threshold voltage of MOS device. Simulation of devices with suitable tools and models helps us to mimic the device performance. Often errors are possible during selecting the models and regions of probing during simulation of results. This paper investigates the role of interface charges on carrier mobility and other MOSFET parameters. The probing positions for extraction of mobility are optimized by simulating the mobility at various positions along the channel and at various depths in the channel. From simulation results, it is shown that higher mobility is obtained by probing in the middle of the channel, 1 nm below the HfO2–Si interface. The performance of the high-k MOSFET with metal electrode and polysilicon electrode is also compared for various interface state charges.

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Acknowledgments

The authors thank the Director, CEERI for his encouragement during the course of this work. Financial support from Council of Scientific and Industrial Research (CSIR), New Delhi, India, under Emeritus Scientist research scheme is greatly acknowledged. The authors would also like to thank members of Sensors and Nanotechnology Group, CEERI, Pilani for their insightful discussions.

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Authors and Affiliations

  1. Birla Institute of Technology and Science (BITS), Pilani, 333031, India

    Saptarshi Basak

  2. Uniphos Envirotronic Pvt. Ltd, Vapi, 396195, Gujarat, India

    Shashank Nagaraj

  3. Central Electronics Engineering Research Institute, Pilani, 333031, India

    Rajendra K. Nahar

Authors
  1. Saptarshi Basak
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  2. Shashank Nagaraj
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  3. Rajendra K. Nahar
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Corresponding author

Correspondence to Shashank Nagaraj .

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Editors and Affiliations

  1. , Electronics and Communication Engg., B.N.M. Institute of Technology, 12 Main, 27th Cross, BSK II stage, Bangalore, 560070, Karnataka, India

    Veena S. Chakravarthi

  2. , Electronics & Communication Engineering, B.N.M. Institute of Technology, 12 Main, 27th Cross, BSK II stage, Bangalore, 560070, Karnataka, India

    Yasha Jyothi M. Shirur

  3. , Telecomminication Engineering, B.N.M. Institute of Technology, 12 Main, 27th Cross, BSK II stage, 560070, 560070, Karnataka, India

    Rekha Prasad

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Basak, S., Nagaraj, S., Nahar, R.K. (2013). Simulation and Optimization of Channel Mobility in High-k/Metal Gate Nanoscale MOSFETs. In: Chakravarthi, V., Shirur, Y., Prasad, R. (eds) Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013). Lecture Notes in Electrical Engineering, vol 258. Springer, India. https://doi.org/10.1007/978-81-322-1524-0_30

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  • DOI: https://doi.org/10.1007/978-81-322-1524-0_30

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  • Publisher Name: Springer, India

  • Print ISBN: 978-81-322-1523-3

  • Online ISBN: 978-81-322-1524-0

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