Abstract
Binary multiplier is one of the most time and power consuming architectures in an ALU. The performance efficiency of complex computations is determined by the multiplier algorithm used. Design of an efficient multiplier thus becomes important. An attempt has been made to implement an efficient multiplier using ancient computational techniques using charge recovery logic. This circuit is compared against the existing vedic multiplier circuits designed using conventional CMOS logic, to validate our claim. A 4 × 4 vedic multiplier using 2 N-2P type of charge recovery logic structure is implemented. The design and verification have been done using industry standard SPICE tools. The simulation results depict reduction in the average power consumption by 77.66 %.
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© 2013 Springer India
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Appasaheb, B.R., Kanchana Bhaaskaran, V.S. (2013). Design and Implementation of an Efficient Multiplier Using Vedic Mathematics and Charge Recovery Logic. In: Chakravarthi, V., Shirur, Y., Prasad, R. (eds) Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013). Lecture Notes in Electrical Engineering, vol 258. Springer, India. https://doi.org/10.1007/978-81-322-1524-0_15
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DOI: https://doi.org/10.1007/978-81-322-1524-0_15
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