Abstract
Power minimization is the most required criteria in today’s world of electronics. Reversible logic provides an aid for low power. Fault-tolerant design is the one that enables a system to continue operation, possibly at a reduced level (degradation), rather than failing completely, when some part of the system fails. This helps in serving many safety critical applications. This paper provides a survey of an overview of latest advancements in research of reversible logic techniques at fault-tolerant level. It gives an overview of the methodologies used in the reversible engineering and the fault-tolerant gates used in them. An attempt is made to give a survey of the techniques used in different combinational logics and briefing them.
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References
Landauer R (1961) Irreversibility and heat generation in the computing process. IBM J Res Dev 5:183–191
Bennett CH (1973) Logical reversibility of computation. IBMJ Res Dev 17:525–532
Toffoli T (1980) Reversible computing. In: automata, languages and programming, Verlag, Berlin, pp 632–644
Rahman R, Jamal L, Babu HMH (2011) Design of reversible fault tolerant programmable logic arrays with vector orientation. Int J Inf Commun Technol Res 1(8) (ISSN-2223-4985)
Mitra SK, Chowdhury AR (2012) Minimum cost fault tolerant adder circuits in reversible logic synthesis. IEEE conference 25th international conference on VLSI design (VLSID), 7–11 Jan 2012, pp 334–339
Parhami B (2006) Fault tolerant reversible circuits. In: proceedings of 40th Asimolar conference signals, systems, and computers, Pacific Grove, CA, pp 1726–1729
Sinha HP, Syal N (2012) Design of fault tolerant reversible multiplier. Int J Soft Comput Eng (IJSCE) 1(6):120–124 ISSN: 2231-2307
Bhagyalakshmi HR, Venkatesha MK (2010) Optimized reversible BCD adder using new reversible logic gates. J Comput 2(2):28–32 ISSN 2151-9617
Kaur P, Dhaliwal BS (2012) Design of fault tolerant full Adder/Subtractor using reversible gates. IEEE conference international conference on computer communication and informatics (ICCCI) Coimbatore, India, 10–12 Jan 2012, pp 1–5
Babazadeh S, Haghparast M (2012) Design of a nanometric fault tolerant reversible multiplier circuit. J Basic Appl Sci Res 2(2):1355–1361 ISSN 2090-4304
Islam MDS, Begum Z (2008) Reversible logic synthesis of fault tolerant carry skip BCD adder. J Bangladesh Acad Sci 32(2):193–200
Haghparast M (2008) Design of a novel fault tolerant reversible full adder for nanotechnology based systems. World Appl Sci J 3(1):114–118
Bruce JW, Thornton MA, Shivakumaraiah L, Kokate PS, Li X (2002) Efficient adder circuits based on a conservative reversible logic gates. In: proceedings of IEEE computer society annual symposium on VLSI, Pittsburg, PA, pp 83–88
E. Fredkin and T. Toffoli, “Conservative logic”, Intl. Journal of Theoretical Physics, pp. 219-253, 1982
Ali MB (2012) Optimized design of carry skip BCD adder using new FSNG reversible logic gates. IJCSI Int J Comput Sci Issues 9(4), (3):424–431
Feynman R (1985) Quantum mechanical computers. Opt News 11:11–20
Perkowsi M, Jozwiak L, Kerntopf P, Al-Rabadi A, Coppoa A, Buller Song AX, Khan MMHA, Yanushkevich S, Shmerko VS, Chzazowska-Jeske M (2001) A general decomposition for reversible logic. In: Proceeding RM, Starkville, pp 119–138
Polian I, Hayes JP (2010) Advanced modeling of faults in reversible circuits. IEEE conference, design and test symposium (EWDTS), pp 376–381
Islam MS, Rafiqul Islam M (2005) Minimization of reversible adder circuits. Asian J Inf Technol 4(12):1146–1151
Bharathi M, Neelima K (2012) Scope of reversible engineering at gate-level: fault-tolerant combinational adders. Int J VLSI Des Commun Syst (VLSICS) 3(2):85–98
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Poornima, M., Suma, M.S., Palecha, N., Malavika, T. (2013). Fault-Tolerant Reversible Logic for Combinational Circuits: A Survey. In: Chakravarthi, V., Shirur, Y., Prasad, R. (eds) Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013). Lecture Notes in Electrical Engineering, vol 258. Springer, India. https://doi.org/10.1007/978-81-322-1524-0_12
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DOI: https://doi.org/10.1007/978-81-322-1524-0_12
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