Abstract
In this paper, we present the high-speed reconfigurable coprocessor for the next-generation communication system, which is highly reliable and more accurate with less delay. The proposed high-speed reconfigurable coprocessor can be easily implemented using various standard operations such as bit shuffle operation, convolutional encoding, fast Fourier transform, interleaving, modulation, scrambling, shift-XOR array, Viterbi decoding, and several other function using the proposed design. The coprocessor has been modeled using VHDL, and synthesis has been performed on model-sim. The gate count is of about 34,000 and critical path of about 0:16 μm technology. The performance comparisons shows that the number of clock cycles can be reduced about 48 % for scrambling and 84 % for convolutional encoding compared with existing DSPs. From the results, the performance of the proposed coprocessor is better compared to conventional DSP (SC140) in terms of number of clocks per cycle.
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Mallikarjunaswamy, S., Nataraj, K.R., Rekha, K.R. (2014). Design of High-Speed Reconfigurable Coprocessor for Next-Generation Communication Platform. In: Sridhar, V., Sheshadri, H., Padma, M. (eds) Emerging Research in Electronics, Computer Science and Technology. Lecture Notes in Electrical Engineering, vol 248. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1157-0_7
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DOI: https://doi.org/10.1007/978-81-322-1157-0_7
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