Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction

  • Sushil Bhushan
  • Saurabh Khandelwal
  • Balwinder Raj
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 202)

Abstract

FinFET are more versatile than traditional single-gate field effect transistors because it has two gates that can be controlled independently. Usually, the second gate of FinFET is used to dynamically control the threshold voltage of the first gate in order to improve circuit performance and reduce leakage power. A self-controllable-voltage-level (SVL) circuit which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in standby mode was developed. This SVL circuit can drastically reduce standby leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. In this paper we propose new leakage power reduction techniques namely series LSVL (lower self controlled voltage level) and after using it, leakage power reduces 20 % for every increment of series transistor in lower ground connection. Leakage is found to contribute more amount of total power consumption in power-optimized FinFET logic circuits. This paper mainly deal with the various logic design styles to obtain the Leakage power savings through the judicious use of FinFET logic styles using NOR based design at 45 nm technology. FinFET circuits are superior in performance and produce less static power when compared to 32 nm circuits. FinFET can be designed at 32 nm. Finally, implementation of the schematics in CMOS NOR MODE, SG MODE, IG MODE, IG/LP MODE, LP MODE of NOR based FINFET is simulated by cadence virtuoso tools version 6.1 to obtain Leakage Power and Power Dissipation. By applying this we obtain 88 % Leakage power savings through the judicious use of FinFET logic styles having NOR based design at 45 nm technology.

Keywords

CMOS scaling Low power FinFET DG devices Series LSVL 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Michael C. Wang. “Independent-Gate FinFET Circuit Design Methodology”. IAENG International Journal of Computer Science, 37:1, IJCS_37_1_06.Google Scholar
  2. Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano, and Tomochika Harada, “A Self Controllable-Voltage-Level (SVL) Circuit for Low-Power, High-Speed CMOS Circuits” ESSCIRC 2002.Google Scholar
  3. Nirmal, Vijaya Kumar , Sam Jabaraj. “NAND GATE USING FINFET FOR NANOSCALE TECHNOLOGY”. International Journal of Engineering Science and Technology Vol. 2(5), 2010, 1351-1358.Google Scholar
  4. Brian Swahn and Soha Hassoun, “Gate Sizing: FinFETs vs 32nm Bulk MOSFETs”. DAC 2006,July 24–28, 2006, San Francisco, California, USA. Copyright 2006 ACM 1-59593-381-6/06/0007 …$5.00.Google Scholar
  5. E. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong. “Device scaling limits of Si MOSFETs and their application dependencies”. Proc. IEEE, 89(3):259–288, (2001). Google Scholar
  6. Etienne Sicard, Sonia Delmas, “Basics of CMOS cell design” book, (2006). Google Scholar
  7. T.-J. King, “FinFETs for nanoscale CMOS digital integrated circuits”. In Proc. Int. Conf. Computer-Aided Design, pages 207–210, (2005). Google Scholar
  8. L. Wei, Z. Chen, and K. Roy, “Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs.” In Proc. IEEE Int. SOI Conf., pages 82–83, (1997).Google Scholar
  9. W. Zhang, J. G. Fossum, L. Mathew, and Y. Du, “Physical insights regarding design and performance of independent-gate FinFETs”. IEEE Electronic Device Lett, 52(10):2189–2206, (2005). Google Scholar
  10. Anish Muttreja, Niket Agarwal and Niraj K. Jha, “CMOS logic design with independent-gate FinFETs” ©2007 IEEE Google Scholar
  11. E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C.-T. Chuang, K. Bre, and R. Puri. “Turning silicon on its edge.” IEEE Circuits and Devices Magazine, 20(1):20–31, (2004). Google Scholar
  12. I. Aller. “The double-gate FinFET: Device impact on circuit design.” In Proc. Int. Solid-State Circuits Conf., pages 14–15 (and visual supplements, pp. 655–657), (2003).Google Scholar
  13. P. Beckett, “A fine-grained reconfigurable logic array based on double gate transistors.” In Proc. IEEE Int. Field-Programmable Technology Conf., pages 260–267, (2002).Google Scholar
  14. Randy W. Mann and Benton H. Calhoun, “New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm” 2010, IEEE proceeding on 11th Int’l Symposium on Quality Electronic DesignGoogle Scholar
  15. Zhanping Chen, Liqiong Wei and Kaushik Roy , “REDUCING GLITCHING AND LEAKAGE POWER IN LOW VOLTAGE CMOS CIRCUITS” , (1997). ECE Technical Reports. Paper 85. http://docs.lib.purdue.edu/ecetr/85.Google Scholar

Copyright information

© Springer India 2013

Authors and Affiliations

  • Sushil Bhushan
    • 1
  • Saurabh Khandelwal
    • 1
  • Balwinder Raj
    • 2
  1. 1.I.T.M UniversityGwaliorIndia
  2. 2.N.I.TJalandharIndia

Personalised recommendations