SDRAM Controller for Retention Time Analysis in Low Power Signal Processor
The SDRAM requires the refreshing at every refresh time to maintain the data, and this operation consumes power. Because the power consumption of the processor is decreased, the power cosnumption on the SDRAM is taking large portion of the total power consumption. The refresh time can be expanded because the retention time and power consumption can be changed. In this paper we introduce the SDRAM controller which enables the analysis of the retention time for the power redectoin purpose.
KeywordsLow-power design Resilient design SDRAM controller
This study was supported by Seoul National University of Science and Technology.
- 2.Lee SH, Hong SH, Oh JH, Choi YK, Bae DI, Park SH, Roh BH, Chung TY, Kim K (2003) Improvement of data retention time using DRAM cell with metallic shield embedded (MSE)-STI for 90 nm technology node and beyond. Eur Solid-State Device Res 151–154Google Scholar
- 3.Weber A, Birner A, Krautschneider W (2005) Data retention analysis on individual cells of 256 Mb DRAM in 110 nm technology. Solid-State Device Research Conference, pp 185–188Google Scholar
- 4.Cho MH, Shin C, Liu TJK (2009) Convex channel design for improved capacitorless DRAM Retention Time. Simul Semicond Process Devices 1–4Google Scholar
- 5.Liu J (2012) RAIDR: retention-aware intelligent DRAM refresh, Computer architecture (ISCA). International Symposium on Computer Architecture (ISCA), pp 1–12Google Scholar