Design of High Security and Performance System for Storage Devices Using AES

  • Vinodkumar I. Bellikatti
  • S. Chetan
  • Shivaputra
  • K. S. Kushal
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 174)


“All our dreams can’t be translated into reality. But they can act as foundation stone for our glorious future”

As the technology of communication and storage improves, it needs high security and performance in both software & hardware. This paper describes the design of effective security system for implementing it to encrypt or decrypt the data in storage device. In this paper we are using O’Driocells matrix for mapping & inverse mapping that is used in S-Box calculation which reduces the total no of 1’s to 51 which is less than previously published paper[5] and Mixcolumn is implemented using Combinational logic method instead of Xtime look up table[LUT]. Hence it is effective in terms of speed, low power and high performance. We proposed pipelined AES architecture that can offer low power and high throughput to increase the efficiency.


AES Encrypt/decrypt FDE ATM switch 


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  1. 1.
    Daemen, J., Rijmen, V.: AES Proposal: Rijndael (Version 2). NIST AES,,
  2. 2.
    NIST Federal Information Processing Standards (FIPS PUB 197) Advanced Encryption Standard (November 2001),
  3. 3.
    CAST, Advanced Encryption Standard Core,
  4. 4.
    Elbirt, A., Yip, W., Chetwynd, B., Paar, C.: An FPGAbased performance evaluation of the AES block cipher candidate algorithm finalists. IEEE Trans. of VLSI Systems 9(4), 545–557 (2001)CrossRefGoogle Scholar
  5. 5.
    ThongKhome, K., Thanavijitpun, C.: FPGA Design of AES C Architecture for Portable Hard DiskGoogle Scholar
  6. 6.
    Kim, C.H.: Improved Differential Fault Analysis on AES Key ScheduleGoogle Scholar
  7. 7.
    Wong, M.M., Wong, M.L.D.: A High Throughput Low Power Compact AES S-box Implementation using Composite Field Arithmetic and Algebraic Normal Form RepresentationGoogle Scholar
  8. 8.
    Rijmen, V.: Efficient implementation S-box,
  9. 9.
    Jutla, C., Kumar, V., Rudra, A.: On the Complexity of Isomorphic Galois Field Transforms. IBM Research Report, vol. RC22652, W0211–W0243 (November 2002)Google Scholar
  10. 10.
    Chantarawong, S., Noo-intara, P., Choomchuay, S.: An Architecture for S-Box Computation in the AES. In: Proc. of Information and Computer Engineering Workshop 2004 (ICEP 2004), pp. 157–162 (2004)Google Scholar
  11. 11.
    Hodjat, A., Verbauwhede, I.: Minimum Area Cost for a 30 to 70 Gbits/s AES ProcessorGoogle Scholar
  12. 12.
    Jing, M.-H., Chen, J.-H., Chen, Z.-H.: Diversified MixColumn Transformation of AESGoogle Scholar

Copyright information

© Springer India 2013

Authors and Affiliations

  • Vinodkumar I. Bellikatti
    • 1
  • S. Chetan
    • 2
  • Shivaputra
    • 2
  • K. S. Kushal
    • 1
  1. 1.Dept. of M.Tech [VLSI Design & Embedded System]Dr. Ambedkar Institute of TechnologyBangaloreIndia
  2. 2.Dept. of Electronics & CommunicationDr. Ambedkar Institute of TechnologyBangaloreIndia

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