Abstract
This paper shows external interface of Gmicro/300 which is a high performance 32-bit microprocessor based on the TRON architecture. External interface has block-fetch function to achieve high- performance and address monitor function to keep internal cache’s consistency on multi-CPU system. Block fetch has 64 Mbytes/second transmission rate at a 20 MHz CPU machine clock.
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References
K. Sakamura, “Architecture of the TRON VLSI CPU”, IEEE Micro, April 1987, pp. 17–31.
A. J. Smith, “Cache Memories”, Computing Survey, Vol. 14, No. 3, September 1982.
K Sakamura, “TRON VLSI CPU: Concepts and Architecture”, TRON Project 1987, Springer-Verlag, pp. 200–238.
“MC6820 32-Bit Microprocessor User’ Manual”, MOTOROLA Inc., 1984.
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© 1988 Springer-Verlag Tokyo
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Kitahara, T., Yuhara, M., Fujihira, A., Mitsuhashi, M., Itoh, M. (1988). High Performance Bus Interface of Gmicro/300. In: Sakamura, K. (eds) TRON Project 1988. Springer, Tokyo. https://doi.org/10.1007/978-4-431-68081-9_22
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DOI: https://doi.org/10.1007/978-4-431-68081-9_22
Publisher Name: Springer, Tokyo
Print ISBN: 978-4-431-68083-3
Online ISBN: 978-4-431-68081-9
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