A Floating Point Processing Unit for the Gmicro CPU

Abstract

This paper describes the architecture and implementation of a newly developed floating point processing unit (FPU). It was developed as a high performance 32-bit coprocessor of the 32-bit Gmicro microprocessor, which satisfies the IEEE 754 Standard for Binary Floating-Point Arithmetic.

High performance was achieved by the high speed coprocessor’s interface with the Gmicro CPU and the pipeline processing. The coprocessor’s interface was designed to minimize CPU-FPU communication overhead caused by transferring commands, operands and coprocessor information. Furthermore, to improve operation speed, the FPU performs pipeline processing named command pipeline. The FPU has three main elements, the bus control unit, format conversion unit, and execution control unit. In order to perform high speed calculations, each element in the chip is designed to operate in parallel. Thus the FPU command pipeline operation can execute up to three instructions concurrently. In addition to pipeline processing, the FPU has a powerful execution control unit. It contains a multiplier and two arithmetic units; one is used for exponent value calculations, and the other for mantissa value calculations.

As a result, the FPU executes floating point addition in 0.5 µs and floating point multiplication in 0.45 µs at a 20-MHz clock rate. The FPU with the Gmicro CPU is expected to achieve 4 MWIPS performance.