Abstract
The 32 bit microprocessor GMICRO/1OO is based on the TRON architecture specification. The chip will be used in a small system that does not require a memory management function. The GMICRO/1OO supports variable length bit field instructions in full option so that the chip can handle bitmap operation at high speed. The chip has a 5-stage pipeline scheme. A dynamic branch prediction mechanism was chosen in order to reduce the performance degradiation caused by branch instructions. The effect of dynamic branch prediction was evaluated by two bench mark tests. The results of the bench mark showed improvements of 5 to 10 percent with the branch prediction scheme.
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References
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© 1987 Springer-Verlag Tokyo
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Tomisawa, O., Yoshida, T., Matsuo, M., Shimizu, T., Enomoto, T. (1987). Design Considerations of the Gmicro/100. In: Sakamura, K. (eds) TRON Project 1987 Open-Architecture Computer Systems. Springer, Tokyo. https://doi.org/10.1007/978-4-431-68069-7_19
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DOI: https://doi.org/10.1007/978-4-431-68069-7_19
Publisher Name: Springer, Tokyo
Print ISBN: 978-4-431-68071-0
Online ISBN: 978-4-431-68069-7
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