Abstract
In a hierarchical VLSI design, the block-level layout design is called ‘chip floor plan’. This paper presents a semi-automatic VLSI chip floor plan program CHAMP, which utilizes a color graphic terminal to the fullest. It has an automatic initial placement and semi-automatic block packing procedures. In the chip floor plan problem, because of the variety of block sizes and shapes, it is very difficult to minimize the chip area by only an automatic process using a computer. Consequently, in most cases, the optimum solution is not obtained without the help of a human designer. To facilitate the manual optimization process, CHAMP is provided with a set of interactive commands using a color graphic terminal. In this paper, chip floor plan program CHAMP is described, in which its interactive facilities are emphasized, and the application results are discussed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
C. S. Horng and M. Lie, “An automation/interactive layout planning system for arbitrarily-sized rectangular building blocks,” Proc. 18th Design Automation Conference, pp. 293-300, June 1981.
R.H.J.M. Otten, “Automatic floorplan design,” Proc. 19th Design Automation Conference, pp. 261-267, June 1982.
W. R. Heller, G. Sorkin and K. Maling, “The planar package planner for system designer,” Proc. 19th Design Automation Conference, pp. 253-260, June 1982.
K. Maling, S. H. Mueller and W. R. Heller, “On finding most optimal rectangular package plans,” Proc. 19th design automation Conference, pp. 663-670, June 1982.
A. Leblond, “CAF: A computer-assisted floorplanning tool,” Proc. 20th Design Automation Conference, pp. 747-753, June 1983.
T. Sudo, T. Ohtsuki and S. Goto, “CAD systems for VLSI in Japan,” Proc. of IEEE, Vol. 71, No. 1, pp. 129–143 (January 1983).
T. Adachi, H. Kitazawa, M. Nagatani and T. Sudo, “Hierarchical top down layout design method for VLSI chip,” Proc. of 19th Design Automation Conference, pp. 785-791 (June 1982).
K. Ueda, “Placement algorithm for logic modules,” Electron. Lett., 10, 10, pp. 206–208 (1974).
K. Ueda and H. Kitazawa, “Algorithm for VLSI chip floor plan,” Electron. Lett., 19, 3, pp. 77–78 (1983).
H. Kitazawa and K. Ueda, “Chip area estimation method for VLSI chip floor plan,” Electron. Lett., 20, 3, pp. 137–139 (1984).
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1985 Springer-Verlag Tokyo
About this paper
Cite this paper
Ueda, K., Kitazawa, H., Harada, I. (1985). Interactive VLSI Chip Floor Design Using Color Graphics. In: Kunii, T.L. (eds) Frontiers in Computer Graphics. Springer, Tokyo. https://doi.org/10.1007/978-4-431-68025-3_21
Download citation
DOI: https://doi.org/10.1007/978-4-431-68025-3_21
Publisher Name: Springer, Tokyo
Print ISBN: 978-4-431-68027-7
Online ISBN: 978-4-431-68025-3
eBook Packages: Springer Book Archive