Skip to main content

Design and Development of Electronic Systems for Quality and Dependability

  • Chapter
  • First Online:
VLSI Design and Test for Systems Dependability
  • 1203 Accesses

Abstract

In this chapter, we quickly walk through the development process of electronic systems that use VLSIs as key parts to provide a background and introduction to the rest of this book. Setting a good goal for a development is not simple to begin with, and the task to get there is often more demanding than it appears at the beginning. The importance of project management and role played by the project manager is first pointed out along with the need to clearly define and document the system requirements specification . Besides the performance and dependability, other aspects of the design goal such as cost, timeline, and compliance are discussed as well, in recognition of the reality of product development. After all, the one who heads up the development is in a position to account for the quality of product throughout its life and return on the investment in the development as well. The multiple phases of the life of an electronic system are described: design, verification, prototyping, test, validation/certification, operation in the field, and finally, retirement. Among these, the specific process in the design of risk analysis and dependability engineering is highlighted as the central topic of this book. Simultaneous assessment of the outcome of possible systems failures and economic viability of the product being pursued is elaborated. Some of the specific technologies developed in the present work, CREST DVLSI Program sponsored by JST, are referred to as possible solutions to problems encountered in designing dependability in future electronic systems to address immediate market needs as well as far-reaching issues such as the IoT (Internet of Things ) and system of systems .

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 189.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 249.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 249.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

Notes

  1. 1.

    It is customary to conduct the development of a custom-built system under a business contract between the user and the builder. The contract covers SRS, price (for the system, NRE, warranty, maintenance and services, parts supply), delivery, payment conditions, compliance, provisions for the breach of contract terms, and so forth. Such contracts often address the ownership of intellectual properties that underlie or arise/derive from the development. Those who want to be engaged in product development are strongly advised to learn about the management of contractual development project.

References

  1. Project Management Institute, “What is Project Management?” http://www.pmi.org/, https://www.pmi.org/about/learn-about-pmi/what-is-project-management

  2. Microsoft Store URL: “Microsoft Project,” https://www.microsoftstore.com/store/msusa/en_US/cat/Project/categoryID.69407700

  3. D. Patterson, J. Hennessy, Computer organization and design, the hardware/software interface, ARM edn. (U.S.A, Morgan Kauffman, Cambridge, 2016)

    MATH  Google Scholar 

  4. Refer to EDA (Electronic Design Automation) tool vendor websites, for example: Synopsis, Cadence, Mentor Graphics, for example

    Google Scholar 

  5. SPICE, A circuit simulator that originates at the University of California at Berkeley and has disseminated by firms specializing in design tools. Tools are available from vendors [4]

    Google Scholar 

  6. Refer to the websites of Mathworks, for example, for ‘model-based’ design tools: https://www.mathworks.com/products/matlab.html?s_tid=hp_products_matlab

  7. Refer to the websites of ‘multi-physics’ simulator vendors, ANSYS, COMSOL, for example: http://www.ansys.com/products/multiphysics https://www.comsol.jp/multiphysics

  8. Wikipedia, “Bill of Materials,” https://en.wikipedia.org/wiki/Bill_of_materials

  9. There is abundant information available on the internet net about this topic. Please throw key words such as “manufacturing bom” at a search engine. Most are offered commercially

    Google Scholar 

  10. ISO Website, “Standards Catalogue, ISO/IEC JTC 1/SC 7- Software and systems engineering” http://www.iso.org/iso/iso_catalogue/catalogue_tc/catalogue_tc_browse.htm?commid=45086

  11. FDA, “General Principles of Software Validation; Final Guidance for Industry and FDA Staff,” FDA website: http://www.fda.gov/RegulatoryInformation/Guidances/ucm085281.htm

  12. FDA, “Software As a Medical Device (SAMD): Clinical Evaluation, FDA Website”; http://www.fda.gov/downloads/MedicalDevices/DeviceRegulationandGuidance/GuidanceDocuments/UCM524904.pdf

  13. International Standards, IEC/ISO 31010, “Risk management -Risk assessment techniques,” http://www.iso.org/iso/catalogue_detail?csnumber=51073

  14. For example, Dr. Michael Stamatelatos, “Probabilistic Risk Assessment: What is it and Why is it worth performing?” http://www.hq.nasa.gov/office/codeq/qnews/pra.pdf. The internet provides rich reference to PRA which is worth for anyone who is interested in building dependability in electronic products to take time going over. A lot of consultancy firms offer help in risk analysis as well. FDA

  15. International Standards, ISO 11231:2010, “Space Systems—Probabilistic risk assessment—PRA,” http://www.iso.org/iso/home/store/catalogue_tc/catalogue_detail.htm?csnumber=50302

  16. International Standard, IEC 61508, “Functional safety of electrical/electronic/programmable electronic safety-related systems,” http://www.iec.ch/functionalsafety/

  17. International Standard, IEC 61508-5 “Functional safety of electrical/electronic/programmable electronic safety-related systems—Part 5: Examples of methods for the determination of safety integrity levels,” https://webstore.iec.ch/publication/5519

  18. International Standard, ISO 26262, Road-vehicles—Functional safety,”

    Google Scholar 

  19. T. Grossman, J.L. Livingstone, The portable MBA in finance and accounting, 4th edn, Wiley, New York, Sept 2009; see also: R.C. Higgins, Analysis for Financial Management, 10th ed., McGraw-Hill Education, December, 2011 for return-on-investment performance indexes similar but with different definitions

    Google Scholar 

  20. Refer to the Intel product support website at the following. http://www.intel.com/content/www/us/en/support/processors/000007093.html

  21. E. Ibe et al., Radiation-Induced Soft Errors, Section 3.1 of this book

    Google Scholar 

  22. H. Kawaguchi, Soft-Error Tolerant SRAM Cell Layout, Section 3.2 of this book

    Google Scholar 

  23. K. Kobayashi, Radiation-Hard Flip-Flops, Section 3.3 of this book

    Google Scholar 

  24. Y. Mitsuyama, Soft-Error-Tolerant Reconfigurable Architecture, Section 3.4 of this book

    Google Scholar 

  25. M. Sugihara, Simulation and Design Techniques for Memory Systems, Section 3.5 of this book

    Google Scholar 

  26. M. Nagata et al., “Electromagnetic Compatibility of CMOS ICs,” Section 4.1 of this book

    Google Scholar 

  27. M. Nagata, “Electromagnetic Noise Immunity in Memory Circuits,” Section 4.2 of this book

    Google Scholar 

  28. M. Nagata, “Power Noise of IC Chips in Assembly and Its Mitigations,” Section 4.3 of this book

    Google Scholar 

  29. N. Yamasaki, “Responsive Link for Noise-tolerant Real-time Communications,” Section 4.4 of this book

    Google Scholar 

  30. H. Onodera, “Overview of Device Variations,” Section 5.1 of this book

    Google Scholar 

  31. H. Onodera, “Monitoring and Compensation for Variations in Device Characteristics,” Section 5.2 of this book

    Google Scholar 

  32. Y. Miura et al., “Highly Accurate Delay-Time Measurement by an On-Chip Circuit,” Section 5.3 of this book

    Google Scholar 

  33. T. Sato et al., “Timing-Error-Sensitive Flip-Flop for Error-Prediction,” Section 5.4 of this book

    Google Scholar 

  34. K. Nii et al., “Fine-Grain Assist Bias Control for Dependable SRAM,” Section 5.5 of this book Discussed in this chapter are general review of the topic (Sections 5.1 and 5.2), on-chip delay-time measurement (Section 5.3), timing-error-sensitive flip-flop for error prediction (Section 5.4) and fine-grained voltage assist for SRAM that works against variations (Section 5.5)

    Google Scholar 

  35. T. Sato et al., “Time-Dependent Degradation in Device Characteristic,” Section 6.1 of this book

    Google Scholar 

  36. S. Tanakamaru et al., “Degradation of Flash Memories and Signal Processing for Dependability,” Section 6.2 of this book

    Google Scholar 

  37. Y. Sato et al., “In-Field Monitoring of Device Degradation for Predictive Maintenance,” Section 6.3 of this book

    Google Scholar 

  38. M. Yoshimoto et al., “A Reconfigurable SRAM Cache Design for Wide-Range Reliable Low-Voltage Operation,” Section 6.4 of this book

    Google Scholar 

  39. H. Shimada et al., “Runtime Self Reconstruction for Soft/Hard Fault Toleration,” Section 6.5 of this book

    Google Scholar 

  40. G. Moor, Cramming More Components onto Integrated Circuits. Electron. Mag. 19, 4 (1965)

    Google Scholar 

  41. For actual trend in the speed of integration, refer, for example, to: Intel Website, “50 years of Moore’s Law,” http://www.intel.com/content/www/us/en/silicon-innovations/moores-law-technology.html

  42. B. David, Understanding Moore’s Law, Four Decades of Innovation, Chapter 4 The Future of Integration, p. 39, CHF Publications, Philadelphia (2006)

    Google Scholar 

  43. M. Koyanagi et al., “Connectivity Issues in 3D Packaging,” Section 8.3 of this book

    Google Scholar 

  44. M. Koyanagi et al., “A 3-D VLSI Architecture for Future Automotive Visual Recognition,” Chapter 26 of this book

    Google Scholar 

  45. On-chip error correction in DRAM from Intelligent Memory is said to be capable of correcting single-bit errors on the fly, “ECC DRAM,” http://www.intelligentmemory.com/ECC-DRAM/DDR3/

  46. S. Tanakamaru, “Design and Application of Dependable Non-Volatile Memory Systems,” Chapter 18 of this book

    Google Scholar 

  47. M. Yoshimoto, “Design of SRAM Resilient against Dynamic Voltage Variations,” Chapter 17 of this book

    Google Scholar 

  48. M. Yoshimoto, “A Low-Latency DMR Architecture with Efficient Recovery Scheme Exploiting Simultaneously Copiable SRAM,” Chapter 25 of this book

    Google Scholar 

  49. Refer, for example, to; Wikipedia, “Dual Modular Redundancy,” https://en.wikipedia.org/wiki/Dual_modular_redundancy

  50. Refer, for example, to; Wikipedia, “Triple Modular Redundancy,” https://en.wikipedia.org/wiki/Triple_modular_redundancy

  51. T. Kuroda et al., “Connectivity in Electronic Packaging,” Section 8.1 of this book

    Google Scholar 

  52. T. Kuroda et al., “Wireless Interconnect in Electronic Systems,” Chapter 21 of this book

    Google Scholar 

  53. H. Ishikuro et al., “Connectivity in Electronic Packaging,” Section 8.2 of this book

    Google Scholar 

  54. H. Ishikuro et al., “Wireless Power Delivery Resilient against Loading Variations,” Chapter 22 of this book

    Google Scholar 

  55. T. Yoneda et al., “Asynchronous Network on Chip,” Section 9.3 of this book

    Google Scholar 

  56. T. Yoneda et al., “Dependable Network-on-Chip Platform for Safety-Critical Automotive Applications,” Chapter 19 of this book

    Google Scholar 

  57. M. Imai et al., “Fault Detection and Reconfiguration in NoC-Coupled Multiple CPU Cores for Deadline-Specified Periodical Tasks,” Section 12.5 of this book

    Google Scholar 

  58. K. Kise, “An On-Chip Router Architecture for Multicore Processor,” Chapter 20 of this book

    Google Scholar 

  59. Y. Nakabo, “Responsiveness for Hard-Real Time Control,” Section 9.1 of this book

    Google Scholar 

  60. N. Yamasaki et al, “Microprocessor Architecture for Real-Time Processing,” Section 9.2 of this book

    Google Scholar 

  61. N. Yamasaki et al, “Responsive Multithreaded Microprocessor for Hard-Real Time Robotic Applications,” Chapter 24 of this book

    Google Scholar 

  62. H. Hihara et al., “A Re-Configurable Processor Architecture for Space Applications,” Chapter 27 of this book

    Google Scholar 

  63. T. Fujino et al., “The tamper resistance against Malicious Attacks on Security VLSIs,” Section 10.1 of this book

    Google Scholar 

  64. Y. Hori, “Methods for Tampering Cryptographic VLSIs,” Section 10.2 of this book

    Google Scholar 

  65. M. Shiozaki, “Tamper-Resistant Symmetric-Key Cryptographic Circuits,” Section 10.3 of this book

    Google Scholar 

  66. M. Yoshikawa et al., “Verification Methods for Tamper-Resistant VLSI Design,” Chapter 10.4 of this book

    Google Scholar 

  67. K. Nii et al., “A SRAM-Based Physically Unclonable Function for Authentication and Encryption,” Chapter 29 of this book

    Google Scholar 

  68. M. Yoshimura, “A Method for Evaluating Vulnerability to Scan-Based Attacks,” Section 10.6 of this book

    Google Scholar 

  69. Y. Hori, “Evaluation of Tamper Resistance of VLSI, “Section 10.7 of this book

    Google Scholar 

  70. D. Suzuki, “Security Components for Systems-Level Authentication,” Chapter 28 of this book

    Google Scholar 

  71. F. Adachi et al., “Challenges for Dependable Public Wireless Telecommunications,” Section 7.1 of this book

    Google Scholar 

  72. K. Tsubouchi et al., “Challenges for Dependable Air,” Section 7.2 of this book

    Google Scholar 

  73. T. Takagi, “Challenges in Wireless Signal Processing,” Section 7.3 of this book

    Google Scholar 

  74. M. Fujishima, “Broad-Band RF Circuit for Versatile, Dependable Wireless Telecommunications,” Section 7.4 of this book

    Google Scholar 

  75. R. Inagaki et al., “All-Si CMOS Front-End ICs for Multi-Band Micro-/Millimeter-Wave Communications,” Section 7.5 of this book

    Google Scholar 

  76. A. Matsuzawa et al., “Dependable Analog-to-Digital Converter,” Section 7.6 of this book

    Google Scholar 

  77. K. Tsubouchci, “Multimode Frequency-Domain Equalizer for Heterogeneous Wireless System,” Section 7.7 of this book

    Google Scholar 

  78. S. Kameda, “Network Technology for Heterogeneous Wireless System,” Section 7.8 of this book

    Google Scholar 

  79. K. Tsubouchi et al., “Connectivity in Wireless Communications,” Chapter 23 of this book

    Google Scholar 

  80. S. Kameda, “Timing Dependability for Wireless Network,” Section 9.4 of this book

    Google Scholar 

  81. N. Kanekawa, “Historical Review of Faults and Unidentified Future Threats,” Section 12.1 of this book

    Google Scholar 

  82. T. Miyoshi, “Challenges to Dependability at Data Centers,” Section 12.2 of this book

    Google Scholar 

  83. M. Fujita et al., “Post-Silicon Validation and Patchable Hardware for Rectification,” Section 12.3 of this book

    Google Scholar 

  84. S. Kajihara et al., “Logging and Using Field-Test Data for Improved Dependability,” Section 12.4 of this book

    Google Scholar 

  85. H. Takizawa et al., “Checkpoint-Restart in Heterogeneous Multiple-Processor Systems,” Section 12.6 of this book

    Google Scholar 

  86. K. Takayama at al., “Verification and Test Coverage,” Section 11.1 of this book

    Google Scholar 

  87. M. Fujita et al., “Design Errors and Formal Verification,” Section 11.2 of this book

    Google Scholar 

  88. M. Fujita, “Formal Verification and Debugging of VLSI Logic Design for Systems Dependability: Experiments and their Evaluation,” Chapter 14 of this book

    Google Scholar 

  89. H. Yasuura, “Design Automation for Reliability,” Chapter 13 of this book

    Google Scholar 

  90. S. Oho et al., “Virtualization: System-Level Fault Simulation of SRAM Errors in Automotive Electronic Control System,” Chapter 15 of this book

    Google Scholar 

  91. K. Hatayama et al., “Circuit and System Mechanisms for High Field Reliability - DART Technology,” Chapter 16 of this book

    Google Scholar 

  92. M. Inoue et al., “High Quality Delay Testing for In-Field Self-Test,” Section 11.3 of this book

    Google Scholar 

  93. T. Yoneda et al., “Temperature- and Voltage-Variation-Aware Delay Test,” Section 11.4 of this book

    Google Scholar 

  94. L. Young, Telecom Experts Plot a Path to 5G, in IEEE Spectrum IEEE. http://spectrum.ieee.org/telecom/wireless/telecom-experts-plot-a-path-to-5g. Accessed 6 Oct 2015

  95. Refer to Rigaku Corporation website for information regarding X-ray diffraction and X-ray diffractometer. http://www.rigaku.com/en

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Shojiro Asai .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Japan KK, part of Springer Nature

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Asai, S. (2019). Design and Development of Electronic Systems for Quality and Dependability. In: Asai, S. (eds) VLSI Design and Test for Systems Dependability. Springer, Tokyo. https://doi.org/10.1007/978-4-431-56594-9_2

Download citation

  • DOI: https://doi.org/10.1007/978-4-431-56594-9_2

  • Published:

  • Publisher Name: Springer, Tokyo

  • Print ISBN: 978-4-431-56592-5

  • Online ISBN: 978-4-431-56594-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics