Abstract
In this chapter, we present a self-contained security coprocessor architecture that using a “Glitch PUF” and a block cipher, efficiently integrates functions necessary for secure key storage and challenge-response authentication. Based on the fact that a Glitch PUF uses a random logic for the purpose of generating glitches, the presented architecture is designed around a block cipher circuit such that its round functions can be shared with a Glitch PUF as a random logic. As a concrete example, a circuit structure using a Glitch PUF and an AES circuit is presented, and evaluation results for its implementation on FPGA are provided. In addition, a physical random number generator using the same circuit is presented. Evaluation results by the two major test suites for randomness, NIST SP 800-22, and Diehard are provided, proving that the physical random number generator passes the test suites. The self-contained security coprocessor ensures that the software it runs does not contain malicious code, the accessories are genuine, and the network devices it connects to are not cloned ones.
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Notes
- 1.
A Full version was presented at [1] Copyright 2014 IEICE.
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Suzuki, D., Shimizu, K., Fujino, T. (2019). An FPGA Implementation of Comprehensive Security Functions for Systems-Level Authentication. In: Asai, S. (eds) VLSI Design and Test for Systems Dependability. Springer, Tokyo. https://doi.org/10.1007/978-4-431-56594-9_28
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