Design Automation for Reliability

Abstract

For design of dependable VLSI design, we need design automation tools, which are compatible with the existing VLSI design toolchain for hierarchical design from system architecture level to device level. The existing toolchain contains analysis and synthesis tools for cost (area), performance, and power consumption of the VLSI. Since dependability is a new measurement of VLSI system design, new methods of evaluation and optimization of the designed VLSI system should be established. The difficulty of the evaluation and optimization of dependability is caused by variety of measurements, probabilistic phenomena, and hierarchical discontinuity of dependability. In this section, design automation tools for soft error are presented, as an example. Soft error occurs collisions of neutrons. An analysis tool of physical level simulates a process of changes of density of charges caused by the collision. In electric circuit level, the neutron collision is presented as an appearance of temporary unexpected current source in the circuit. Circuit simulators can be used to analyze the effect of the temporary current source. Only huge voltage change, which is a pulse signal larger than logical threshold of gates and bit flip of memory elements, should be considered in the logical circuit level. In logic circuit level, propagation of the pulses should be analyzed. Some pulses may disappear by masking effects of logical gates and flip-flops. Memories have to be analyzed by different approaches utilizing the regularity. In register transfer and system architecture levels, a system error occurs only when the wrong data is read out and used in the subsequent computation process affecting the final output of the VLSI system.