Abstract
We present the calibration of a device simulator for a 0.25 µm CMOS technology using response surface methodology. For this process several measurements for different gate lengths (0.2–4.0 µm) were made. Care was taken to eliminate the statistical variations typical to sub-micron devices by measuring several chips on the the same wafer and taking an average sample. The simulations carried out with the calibrated parameters show an error smaller than 2.4% for both the long-channel and the short-channel device.
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References
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© 1998 Springer-Verlag/Wien
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Grasser, T., Strasser, R., Knaipp, M., Tsuneno, K., Masuda, H., Selberherr, S. (1998). Device Simulator Calibration for Quartermicron CMOS Devices. In: De Meyer, K., Biesemans, S. (eds) Simulation of Semiconductor Processes and Devices 1998. Springer, Vienna. https://doi.org/10.1007/978-3-7091-6827-1_26
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DOI: https://doi.org/10.1007/978-3-7091-6827-1_26
Publisher Name: Springer, Vienna
Print ISBN: 978-3-7091-7415-9
Online ISBN: 978-3-7091-6827-1
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