Abstract
As dynamic RAM cell size is being scaled down, the storage capacitor design becomes more difficult because its capacitance cannot scale as much. The solutions are leading to complex structures which require an accurate description of the fabrication process, making technology CAD (TCAD) simulations necessary We introduce a set of layout-driven TCAD tools to perform capacitance extraction of three-dimensional structures created by rigorous topographic simulation, suitable in the development of new cell configurations. Simulation results are also given and compared with measured data.
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© 1998 Springer-Verlag/Wien
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Martins, R., Sabelka, R., Pyka, W., Selberherr, S. (1998). Rigorous Capacitance Simulation of DRAM Cells. In: De Meyer, K., Biesemans, S. (eds) Simulation of Semiconductor Processes and Devices 1998. Springer, Vienna. https://doi.org/10.1007/978-3-7091-6827-1_20
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DOI: https://doi.org/10.1007/978-3-7091-6827-1_20
Publisher Name: Springer, Vienna
Print ISBN: 978-3-7091-7415-9
Online ISBN: 978-3-7091-6827-1
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