Abstract
Layout dependent stress induced effects on current drivability of 90nm node CMOS devices have been modeled by both performing stress modeling in process simulation and device simulation with stress dependent mobility model. It has been demonstrated that dependence of drive current of both n- and p-MOSFETs on source/drain size is successfully modeled. In addition, with this procedure, the performance improvement with stress engineering such as modifying shallow trench isolation (STI) process and using nitride liner deposition on gate electrodes can be well reproduced.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
T. Ghani et al, IEDM Tech.Dig., pp 978, 2003.
S. Ito et al, IEDM Tech.Dig., pp 247, 2000.
Y. Kanda, IEEE Trans. ED., vol.29, pp.64, 1982.
J. Egley et al, Solid State Electron., vol.36, pp.1653, 1993.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Wien
About this paper
Cite this paper
Fujii, O. et al. (2004). Modeling of Stress Induced Layout Effect on Electrical Characteristics of Advanced MOSFETs. In: Wachutka, G., Schrag, G. (eds) Simulation of Semiconductor Processes and Devices 2004. Springer, Vienna. https://doi.org/10.1007/978-3-7091-0624-2_15
Download citation
DOI: https://doi.org/10.1007/978-3-7091-0624-2_15
Publisher Name: Springer, Vienna
Print ISBN: 978-3-7091-7212-4
Online ISBN: 978-3-7091-0624-2
eBook Packages: Springer Book Archive