CMOS Circuit Performance Enhancement by Surface Orientation Optimization

Abstract

With the advent of novel device structures that can be easily fabricated outside of the traditional (100) plane, it may be advantageous to change the crystal orientation to optimize CMOS circuit performance. The use of alternative surface orientations enhances hole mobility while degrading electron mobility. By optimizing the surface orientation, up to a 15% improvement in gate delay can be expected. This technique is especially attractive in the FinFET device structure, in which orientation optimization can be performed by trading off layout area.