Abstract
Multimedia applications process streams of values and can often be represented as task graphs. For performance reasons, these task graphs are executed on multiprocessor systems. Inter-task communication is performed via buffers, where the order in which values are written into a buffer can differ from the order in which they are read. Some existing approaches perform inter-task communication via first-in-first-out buffers in combination with reordering tasks and require applications with affine index-expressions. In our previous work, we used circular buffers with a non-overlapping read and write window, such that a reordering task is not required. However, these windows can cause deadlock for cyclic task graphs.
In this paper, we introduce circular buffers with multiple overlapping windows that do not delay the release of locations and therefore they do not introduce deadlock for cyclic task graphs. We show that buffers with multiple overlapping read and write windows are attractive, because they avoid that a buffer has to be selected from which a value has to be read or into which a value has to be written. This significantly simplifies the extraction of a task graph from a sequential application. These buffers are also attractive, because a buffer capacity equal to the array size is sufficient for deadlock-free execution, instead of performing global analysis to compute sufficient buffer capacities. Our case-study presents two applications that require these buffers.
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References
Agarwal, A., et al.: The MIT Alewife machine: architecture and performance. In: Proceedings of the International Symposium on Computer Architecture (ISCA), pp. 2–13. ACM, New York (1995)
Alverson, R., et al.: The Tera computer system. In: International Conference on Supercomputing (ICS), pp. 1–6. ACM, New York (1990)
Bijlsma, T., Bekooij, M.J.G., Smit, G.J.M.: Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphs. In: Proceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS), pp. 140–148. IEEE Computer Society, Los Alamitos, July 2009
Bijlsma, T., et al.: Communication between nested loop programs via circular buffers in an embedded multiprocessor system. In: Proceedings of the International Workshop on Software and Compilers for Embedded Systems (SCOPES), pp. 33–42. ACM, New York (2008)
van den Brand, J.W., Bekooij, M.J.G.: Streaming consistency: a model for efficient MPSoC design. In: Proceedings of the Euromicro Symposium on Digital System Design (DSD), pp. 27–34. IEEE Computer Society, Washington (2007)
Culler, D.E., Gupta, A., Singh, J.P.: Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann, San Francisco (1999)
Gharachorloo, K., et al.: Memory consistency and event ordering in scalable shared-memory multiprocessors. In: Proceedings of the International Symposium on Computer Architecture (ISCA), pp. 15–26. ACM, New York (1990)
Huang, K., Grünert, D., Thiele, L.: Windowed FIFOs for FPGA-based multiprocessor systems. In: Proceedings of the International Conference on Application-Specific Systems, Architectures, and Processors (ASAP), pp. 36–42. IEEE Computer Society, Los Alamitos (2007)
Lee, E.A., Parks, T.M.: Dataflow process networks. Proc. IEEE 83(5), 773–801 (1995)
Oh, J., et al.: Exploiting thread-level parallelism in lockstep execution by partially duplicating a single pipeline. Electron. Telecommun. Res. Inst. (ETRI) J. 30(4), 576–586 (2008)
Turjan, A., Kienhuis, B., Deprettere, E.F.: Realizations of the extended linearization model in the Compaan tool chain. In: Proceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS), pp. 1–24 (2002)
Turjan, A., Kienhuis, B., Deprettere, E.: An integer linear programming approach to classify the communication in process networks. In: Schepers, H. (ed.) SCOPES 2004. LNCS, vol. 3199, pp. 62–76. Springer, Heidelberg (2004). https://doi.org/10.1007/978-3-540-30113-4_6
Turjan, A., Kienhuis, B., Deprettere, E.F.: Translating affine nested-loop programs to process networks. In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), pp. 220–229. ACM, New York (2004)
Verdoolaege, S., Nikolov, H., Stefanov, T.: PN: a tool for improved derivation of process networks. EURASIP J. Adv. Sig. Process. 2007(1), 1–13 (2007)
van der Wolf, P., et al.: Design and programming of embedded multiprocessors: an interface-centric approach. In: Proceedings of the International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), pp. 206–217. ACM, New York (2004)
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Bijlsma, T., Bekooij, M.J.G., Smit, G.J.M. (2019). Circular Buffers with Multiple Overlapping Windows for Cyclic Task Graphs. In: Silvano, C., Bertels, K., Schulte, M. (eds) Transactions on High-Performance Embedded Architectures and Compilers V. Lecture Notes in Computer Science(), vol 11225. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-58834-5_3
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