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v2c – A Verilog to C Translator

  • Rajdeep MukherjeeEmail author
  • Michael Tautschnig
  • Daniel Kroening
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9636)

Abstract

We present v2c, a tool for translating Verilog to C. The tool accepts synthesizable Verilog as input and generates a word-level C program as an output, which we call the software netlist. The generated program is cycle-accurate and bit precise. The translation is based on the synthesis semantics of Verilog. There are several use cases for v2c, ranging from hardware property verification, co-verification to simulation and equivalence checking. This paper gives details of the translation and demonstrates the utility of the tool.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  • Rajdeep Mukherjee
    • 1
    Email author
  • Michael Tautschnig
    • 2
  • Daniel Kroening
    • 1
  1. 1.University of OxfordOxfordUK
  2. 2.Queen Mary, University of LondonLondonUK

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