Dual VP Classes

  • Eric Allender
  • Anna Gál
  • Ian Mertz
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9235)


We consider the complexity class \({\mathsf{ACC}}^1\) and related families of arithmetic circuits. We prove a variety of collapse results, showing several settings in which no loss of computational power results if fan-in of gates is severely restricted, as well as presenting a natural class of arithmetic circuits in which no expressive power is lost by severely restricting the algebraic degree of the circuits. These results tend to support a conjecture regarding the computational power of the complexity class VP over finite algebras, and they also highlight the significance of a class of arithmetic circuits that is in some sense dual to VP.


Complexity Class Prime Power Multiplication Gate Arithmetic Circuit Algebraic Degree 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The first and third authors acknowledge the support of NSF grants CCF-0832787 and CCF-1064785. The second author was supported in part by NSF grant CCF-1018060. We also acknowledge stimulating conversations with Meena Mahajan, which occurred at the 2014 Dagstuhl Workshop on the Complexity of Discrete Problems (Dagstuhl Seminar 14121), and illuminating conversations with Stephen Fenner and Michal Koucký, which occurred at the 2014 Dagstuhl Workshop on Algebra in Computational Complexity (Dagstuhl Seminar 14391). We also thank Igor Shparlinski and our Rutgers colleagues Richard Bumby, John Miller and Steve Miller, for helpful pointers to the literature, as well as helpful feedback from Pascal Koiran and Russell Impagliazzo.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  1. 1.Department of Computer ScienceRutgers UniversityPiscatawayUSA
  2. 2.Department of Computer ScienceUniversity of TexasAustinUSA

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