Time-Varying Square Root

  • Yunong ZhangEmail author
  • Dongsheng Guo


In this chapter, focusing on time-varying square root finding, we propose, generalize, develop, and investigate different ZFs as the error-monitoring functions, which lead to different ZD models. Then, toward the final purpose of field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) realization, the MATLAB Simulink modeling and verification of such different ZD models are shown. Both theoretical analysis and modeling results further substantiate the efficacy of the proposed ZD models for time-varying square root finding.


MATLAB Simulink Model Error-monitoring Function Root Finding Field Programmable Gate Array (FPGA) Application Specific Integrated Circuit (ASIC) 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    IEEE (1985) IEEE standard for binary floating-point arithmetic. IEEE standard 754. IEEE Computer SocietyGoogle Scholar
  2. 2.
    Mathews JH, Fink KD (2005) Numerical methods using MATLAB. Publishing House of Electronics Industry, BeijingGoogle Scholar
  3. 3.
    Lin C (2005) Numerical computation methods. Science Press, BeijingGoogle Scholar
  4. 4.
    Majerski S (1985) Square-rooting algorithms for high-speed digital circuits. IEEE Trans Comput C-34(8):724–733Google Scholar
  5. 5.
    Takahashi D (2000) Implementation of multiple-precision parallel division and square root on distributed-memory parallel computers. In: Proceedings of international workshops on parallel processing, pp 229–235Google Scholar
  6. 6.
    Kong F, Cai Z, Yu J, Li DX (2006) Improved generalized Atkin algorithm for computing square roots in finite fields. Inf Process Lett 98(1):1–5CrossRefzbMATHMathSciNetGoogle Scholar
  7. 7.
    Pineiro JA, Bruguera JD (2002) High-speed double-precision computation of reciprocal, division, square root, and inverse square root. IEEE Trans Comput 51(12):1377–1388CrossRefMathSciNetGoogle Scholar
  8. 8.
    Ercegovac MD, Lang T, Muller JM, Tisserand A (2000) Reciprocation, square root, inverse square root, and some elementary functions using small multipliers. IEEE Trans Comput 49(7):628–637CrossRefMathSciNetGoogle Scholar
  9. 9.
    Zhang YN, Leithead WE, Leith DJ (2005) Time-series Gaussian process regression based on Toeplitz computation of \(O(N^2)\) operations and \(O(N)\)-level storage. In: Proceedings of the 44th IEEE international conference on decision and control, pp 3711–3716Google Scholar
  10. 10.
    Mead C (1989) Analog VLSI and neural systems. Addison-Wesley Longman, BostonCrossRefzbMATHGoogle Scholar
  11. 11.
    Zhang Y, Ma W, Li K, Yi C (2008) Brief history and prospect of coprocessors. China Acad J Electron Publ House 13:115–117Google Scholar
  12. 12.
    Zhang Y, Ke Z, Xu P, Yi C (2010) Time-varying square roots finding via Zhang dynamics versus gradient dynamics and the former’s link and new explanation to Newton-Raphson iteration. Inf Process Lett 110(24):1103–1109CrossRefMathSciNetGoogle Scholar
  13. 13.
    Zhang Y, Yin Y, Guo D, Li W, Ke Z (2013) Different Zhang functions leading to different ZD models illustrated via time-varying square roots finding. In: Proceedings of the 4th international conference on intelligent control and information processing, pp 277–282Google Scholar
  14. 14.
    Zhang Y, Yi C, Guo D, Zheng J (2011) Comparison on Zhang neural dynamics and gradient-based neural dynamics for online solution of nonlinear time-varying equation. Neural Comput Appl 20(1):1–7CrossRefGoogle Scholar
  15. 15.
    Zhang Y, Yi C (2011) Zhang neural networks and neural-dynamic method. Nova Science Publishers, New YorkGoogle Scholar
  16. 16.
    Bushard LB (1983) A minimum table size result for higher radix nonrestoring division. IEEE Trans Comput C-32(6):521–526Google Scholar
  17. 17.
    Trivedi K, Ercegovac M (1977) On-line algorithms for division and multiplication. IEEE Trans Comput C-26(7):681–687Google Scholar
  18. 18.
    Ansari MS, Rahman SA (2011) DVCC-based non-linear feedback neural circuit for solving system of linear equations. Circuits, Syst Signal Process 30(5):1029–1045CrossRefzbMATHGoogle Scholar
  19. 19.
    Shanblatt MA (2005) A Simulink-to-FPGA implementation tool for enhanced design flow. In: Proceedings of the IEEE international conference on microelectronic systems education, pp 89–90Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  1. 1.School of Information Science and TechnologySun Yat-sen UniversityGuangzhouChina

Personalised recommendations