An Approach to Reversible Logic Synthesis Using Input and Output Permutations

Part of the Lecture Notes in Computer Science book series (LNCS, volume 8911)


The problem of reversible logic synthesis has assumed importance with the growing emphasis on low-power design and its relationship to quantum computation. Many synthesis approaches for reversible logic circuits have been reported over the last two decades. For small functions exact solutions that require minimum number of gates can be computed. Otherwise, heuristics have to be applied that are either based on transformations or a direct mapping from a given data structure. Recently, it was shown that significant reduction in the cost of the synthesized circuits can be obtained, if the ordering of the input (or output) lines is changed. The drawback of the approach was that it can only be applied to smaller sized circuits. In this paper, two alternate approaches for obtaining a good ordering of the variables are presented. Given a reversible specification in the form of a truth table or a permutation, both the methods rely on a properly chosen cost function and try to obtain an ordering of the variables that minimizes the cost. The first method uses an evolutionary algorithm (EA) to arrive at a good ordering of the output variables. To avoid long runtimes the EA does not synthesize the circuit after each evolutionary operation. Both the original and the least cost permutations are synthesized using a standard synthesis tool, and the improvement in cost are compared. Experimental results demonstrate the effectiveness of the scheme. The second method uses an encoded multi-valued truth table as the data structure, and tries to minimize cost by considering both input and output variable orderings. Feasible moves are defined and an iterative approach based on simulated annealing (SA) is used to minimize the cost. Here also explicit synthesis is avoided during the process of looking for a good variable ordering.


Reversible logic Evolutionary algorithm Simulated annealing Input permutation Output permutation 


  1. 1.
    Datta, K., Rathi, G., Sengupta, I., Rahaman, H.: Synthesis of reversible circuits using heuristic search method. In: International Conference on VLSI Design, pp. 328–333 (2012)Google Scholar
  2. 2.
    Drechsler, R., Finder, A., Wille, R.: Improving ESOP-based synthesis of reversible logic using evolutionary algorithms. In: Di Chio, C., et al. (eds.) EvoApplications 2011, Part II. LNCS, vol. 6625, pp. 151–161. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  3. 3.
    Fazel, K., Thornton, M.A., Rice, J.: ESOP-based Toffoli gate cascade generation. In: Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 206–209 (2007)Google Scholar
  4. 4.
    Feynman, R.: Quantum mechanical computers. Optic. News 11, 11–20 (1985)CrossRefGoogle Scholar
  5. 5.
    Goldberg, D.: Genetic Algorithms in Search, Optimization, and Machine Learning. Addison-Wesley Professional, Upper Saddle River (1989)zbMATHGoogle Scholar
  6. 6.
    Goldberg, D., Lingle, R.: Alleles, loci and the travelling salesman problem. In: International Conference on Genetic Algorithms, pp. 154–159 (1985)Google Scholar
  7. 7.
    Grosse, D., Wille, R., Dueck, G.W., Drechsler, R.: Exact multiple control Toffoli network synthesis with SAT techniques. IEEE Trans. CAD Integr. Circ. Syst. 28(5), 703–715 (2009)CrossRefGoogle Scholar
  8. 8.
    Gupta, P., Agrawal, A., Jha, N.K.: An algorithm for synthesis of reversible logic circuits. IEEE Trans. CAD Integr. Circ. Syst. 25(11), 2317–2329 (2006)CrossRefGoogle Scholar
  9. 9.
    Khanom, R., Kamal, T., Khan, M.H.A.: Genetic algorithm based synthesis of ternary reversible quantum circuit. In: International Conference on Computer and Information Technology (ICCIT 2008), pp. 270–275 (2008)Google Scholar
  10. 10.
    Li, M., Zheng, Y., Hsiao, M.S., Huang, C.: Reversible logic synthesis through ant colony optimization. In: Design Automation Test in Europe, pp. 208–212 (2010)Google Scholar
  11. 11.
    Maslov, D., Dueck, G.W., Miller, D.M.: Toffoli network synthesis with templates. IEEE Trans. CAD Integr. Circ. Syst. 24(6), 807–817 (2005)CrossRefGoogle Scholar
  12. 12.
    Miller, D.M., Maslov, D., Dueck, G.W.: A transformation based algorithm for reversible logic synthesis. In: Design Automation Conference, pp. 318–323 (2003)Google Scholar
  13. 13.
    Rabaey, J.M.: Low Power Design Essentials. Springer: Series on Integrated Circuits and Systems. Springer, New York (2009)CrossRefGoogle Scholar
  14. 14.
    Rice, J.E., Nayeem, N.: Ordering techniques for ESOP-based Toffoli cascade generation. In: Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 274–279 (2011)Google Scholar
  15. 15.
    Shende, V.V., Shende, A.K., Markov, I.L., Hayes, J.P.: Synthesis of reversible logic circuits. IEEE Trans. CAD Integr. Circ. Syst. 22(6), 710–722 (2003)CrossRefGoogle Scholar
  16. 16.
    Soeken, M., Frehse, S., Wille, R., Drechsler, R.: RevKit: an open source toolkit for the design of reversible circuits. In: De Vos, A., Wille, R. (eds.) RC 2011. LNCS, vol. 7165, pp. 64–76. Springer, Heidelberg (2012). RevKit is available at CrossRefGoogle Scholar
  17. 17.
    Toffoli, T.: Reversible computing. Automata, Languages and Programming. Springer, Tech. Memo-MIT/LCS/TM-151, MIT Lab for Comp. Sci. (1980)Google Scholar
  18. 18.
    Wille, R., Drechsler, R.: BDD-based synthesis of reversible logic for large functions. In: Design Automation Conference, pp. 270–275 (2009)Google Scholar
  19. 19.
    Wille, R., Grosse, D., Dueck, G.W., Drechsler, R.: Reversible logic synthesis with output permutation. In: International Conference on VLSI Design, pp. 189–194 (2009)Google Scholar
  20. 20.
    Wille, R., Grosse, D., Teuber, L., Dueck, G.W., Drechsler, R.: Revlib: an online resource for reversible functions and reversible circuits. In: International Symposium on Multi-Valued Logic, pp. 220–225 (2008)Google Scholar
  21. 21.
    Wille, R., Soeken, M., Przigoda, N., Drechsler, R.: Exact synthesis of Toffoli gate circuits with negative control lines. In: International Symposium on Multi-Valued Logic, pp. 69–74 (2012)Google Scholar
  22. 22.
    Yang, G., Xie, F., Song, X., Hung, W.N.N., Perkowski, M.A.: A constructive algorithm for reversible logic synthesis. In: World Congress on Computational Intelligence, pp. 2416–2421 (2006)Google Scholar
  23. 23.
    Zhang, M., Zhao, S., Wang, X.: Automatic synthesis of reversible logic circuit based on genetic algorithm. In: International Conference on Intelligent Computing and Intelligent Systems (ICIS 2009), pp. 542–546 (2009)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2014

Authors and Affiliations

  1. 1.Department of Computer Science and EngineeringNational Institute of TechnologyShillongIndia
  2. 2.Department of Computer Science and EngineeringIndian Institute of TechnologyKharagpurIndia
  3. 3.Department of Information TechnologyIndian Institute of Engineering Science and Technology, ShibpurHowrahIndia
  4. 4.Institute of Computer ScienceUniversity of BremenBremenGermany
  5. 5.Cyber-Physical SystemsDFKI GmbHBremenGermany

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