Abstract
Although the performance of multi-core processor continues to increase steadily, power consumption with core density at such high level gradually becomes a limiting factor for computing facilities hosting massive servers to expand at even larger scale, especially as we entering the era of many core architecture. In spite of various power management techniques already existed for year, none of them has ever been demonstrated feasible on the real many core platforms since it is until recently the Intel Xeon Phi processor realizes the prospect of many core architecture into product. Along with the Xeon Phi processor, the power management capability has been significantly improved with hardware and software support that the user could analyze the power consumption of the application at fine granularity with sufficient information captured during the runtime by the power monitoring infrastructures implemented on Xeon Phi processor. However, at the time we propose this study, there is no comprehensive investigation to evaluate the power and energy properties of such many core platform when running diverse applications despite of the performance boost.
In this paper, we leverage representative benchmark suites including various parallel workloads, running with OpenMP mode, from diverse domains to evaluate the MIC architecture. With the power measurement ability exposed by Power Management and SCIF interface, the energy can be tracked every 50 ms. The experiments reveal non-intuitive results on the impact of MIC in terms of energy efficiency: (1) for computation intensive workload such as BT and FT in NPB, MC and MD in SHOC, in contrast to our expectation, MIC doesn’t keep improving the system energy efficiency with the increasing threads; (2) for memory intensive application such as IS in NPB and DeviceMemory in SHOC, MIC actually deteriorates the system energy efficiency significantly; (3) for EPCC, which is used to investigate overheads of key OpenMP constructs, the workloads suffer energy efficiency decline mostly caused by the high pressures from the communication among cores.
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Acknowledgments
This work was supported by the National High Technology Research and Development Program (“863” Program) of China under the grant No.2012AA010904.
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Zhao, Q., Yang, H., Wei, G., Luan, Z., Qian, D. (2014). Energy Efficiency Evaluation of Workload Execution on Intel Xeon Phi Coprocessor. In: Yuan, Y., Wu, X., Lu, Y. (eds) Trustworthy Computing and Services. ISCTCS 2013. Communications in Computer and Information Science, vol 426. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-43908-1_34
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DOI: https://doi.org/10.1007/978-3-662-43908-1_34
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