Skip to main content
SpringerLink
Log in

High Signal-to-Noise Ratio DRAM Design and Technology

  • Chapter
VLSI Memory Chip Design

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 5))

  • 1160 Accesses

Abstract

One of the main contributions to DRAM advances is the one-transistor, one-capacitor (1-T) cell, as explained in Chaps. 1 and 3. The cell has been universally used for over 25 years, because it has the highest density. The drawbacks — no gain and the existence of leakage currents in the cell — have been overcome by successive developments in high signal-to-noise (S/N) ratio designs and technologies. Moreover, the multidivision of data lines by using multilevel metal wiring, explained in Chap. 3 has allowed not only a highspeed and low-power array, but also a high S/N array, while limiting the increase in chip area. Without high S/N designs and technologies, the kilobit and megabit eras would not have been developed at all. In the multigigabit era, however, there are many challenges to realizing high S/N cell design to cope with the ever-decreasing cell area and ultra-low-voltage operations. The development of higher-permittivity materials for capacitor dielectric films, while keeping the fabrication process as simple as possible, and the suppression of the random design-parameter variations of MOSFETs, which are prominent below 0.1 μm, are good examples. However, it will be more difficult than ever to accomplish these things, because of fabrication and physical limits.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 179.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 229.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 249.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. K. Itoh, VLSI Memory Design (Baifukan, Tokyo 1994) (in Japanese).

    Google Scholar 

  2. K. Itoh et al., Electrochemical Society Proc. 98–1, 350 (1998).

    Google Scholar 

  3. K. Itoh, “Ultralow-Voltage Memory Circuits”, VLSI ’97 Tutorial, Gramado (Brazil) (1997).

    Google Scholar 

  4. T.C. May, M.H. Woods, “A New Physical Mechanism for Soft Errors in Dynamic Memories”, Proc. Reliab. Physics Symp., pp. 33–40, April 1978.

    Google Scholar 

  5. K. Itoh, in Low Power Design Methodologies, J.M. Rabaey, M. Pedram, Editors (Kluwer, Norwell, MA 1995).

    Google Scholar 

  6. K. Shimotori et al., “A 100 ns 256 K DRAM with Page-Nibble Mode”, ISSCC Dig. Tech. Papers, pp. 228–229, Feb. 1983.

    Google Scholar 

  7. M. Koyanagi et al., “Novel High Density, Stacked Capacitor MOS RAM”, IEDM Tech. Dig., pp. 348, 1978.

    Google Scholar 

  8. H. Sunami et al, IEEE Trans. Electron Devices ED-31, 746 (1984).

    Google Scholar 

  9. N.C.C. Lu, “Advanced Cell Structure for Dynamic RAMs”, IEEE Circuits and Devices Mag., pp. 27–36, Jan. 1989.

    Google Scholar 

  10. T. Ema et al., IEICE Trans. Electron. E76-C(11), 1564 (1993).

    Google Scholar 

  11. S. Kimura et al., IEEE Trans. Electron Devices 37(3), 737 (1990).

    Article  Google Scholar 

  12. M. Sakao et al., “A Capacitor-Over- Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs”, IEDM Ext. Abst., pp. 655–658, Dec. 1–1990.

    Google Scholar 

  13. A. Ishitani et al., IEICE Trans. Electron. E76-C(11), 1564 (1993).

    Google Scholar 

  14. T. Kuroiwa et al., Jpn. J. Appl. Phys. 33–1(9B), 5187 (1994).

    Article  CAS  Google Scholar 

  15. K. Koyama et al., “A Stacked Capacitor with (BaxSr1-x)TiO3 for 256 M DRAM”, IEDM Ext. Abst., pp. 823–826, Dec. 1991.

    Google Scholar 

  16. K. Itoh et al, Proc. IEEE 83(4), 524 (1995).

    Article  Google Scholar 

  17. K. Itoh et al., IEEE J. Solid-State Circuits 32(5), 624 (1997).

    Article  Google Scholar 

  18. K. Ohyu et al., Jpn. J. Appl. Phys. 28(6), 1041 (1989).

    Article  CAS  Google Scholar 

  19. D.S. Yaney et al., IEEE Trans. Electron Devices ED-26, 10 (1979).

    Article  Google Scholar 

  20. K. Takeuchi et al., “Experimental Characterization of a-Induced Charge Collection Mechanism for Megabit DRAM Cells”, Symp. VLSI Tech. Dig. Tech. Papers, pp. 99, May 1987.

    Google Scholar 

  21. Y. Konishi et al., IEEE J. Solid-State Circuits 24, 35 (1989).

    Article  Google Scholar 

  22. M. Aoki et al., IEEE J. Solid-State Circuits 23(5), 1113 (1988).

    Article  Google Scholar 

  23. H. Hidaka et al., IEEE J. Solid-State Circuits 24(1), 21 (1989).

    Article  Google Scholar 

  24. M. Yoshida et al., “Scaled Bit Line Capacitance Analysis using a Three-Dimensional Simulator”, Symp. VLSI Tech. Dig. Tech. Papers, pp. 66–67, 1985.

    Google Scholar 

  25. K.U. Stein, A. Sihling, E. Doering, “Storage Array and Sense/Refresh Circuit for Single-Transistor Memory Cells”, ISSCC Dig. Tech. Papers, pp. 56–57, Feb. 1972.

    Google Scholar 

  26. K. Itoh, IEEE J. Solid-State Circuits 25(3), 778 (1990).

    Article  Google Scholar 

  27. H. Masuda et al, IEEE J. Solid-State Circuits SC-15(5), 846 (1980).

    Article  Google Scholar 

  28. K. Shimotori et al, Trans. IECE J61-C(6), 399 (1978).

    Google Scholar 

  29. Y. Nagayama et al., Trans. IECE J65-C(7), 522 (1982).

    Google Scholar 

  30. J.J. Barnes, J.U. Chan, IEEE J. Solid-State Circuits, SC-15(5), 831 (1980).

    Article  Google Scholar 

  31. P.R. Schroeder, R.J. Proebsting, “A 16 K × 1 Bit Dynamic RAM”, ISSCC Dig. Tech. Papers, pp. 12–13, Feb. 1977.

    Google Scholar 

  32. J.M. Lee et al, “A 80 ns 5 V-only 16 K dynamic RAM”, ISSCC Dig. Tech. Papers, pp. 142–143, Feb. 1979.

    Google Scholar 

  33. S. Fujii et al., “A 50 μA Standby 1 MW × 1 b/256 KW × 4 b CMOS DRAM”, ISSCC Dig. Tech. Papers, pp. 266–267, Feb. 1986.

    Google Scholar 

  34. K. Itoh et al., “An Experimental 1 Mb DRAM with On-Chip Voltage Limiter”, ISSCC Dig. Tech. Papers, pp. 282–283, Feb. 1984.

    Google Scholar 

  35. S. Fujii et al., “A 45 ns 16 Mb DRAM with Triple-Well Structure”, ISSCC Dig.Tech. Papers, pp. 248–249, Feb. 1989.

    Google Scholar 

  36. R. Kraus, K. Hoffmann, IEEE J. Solid-State Circuits 24(4), 895 (1989).

    Article  Google Scholar 

  37. H. Geib et al., IEEE J. Solid-State Circuits 27(7), 1028 (1992).

    Article  Google Scholar 

  38. Y. Watanabe et al., “Offset Compensating Bit-Line Sensing Scheme for High Density DRAMs”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 116–117, 1992.

    Google Scholar 

  39. E.J. Sprogis, Proc. IEEE 1991. Int. Conference on Microelectronic Test Structures 4(1), 103 (1991).

    Article  Google Scholar 

  40. S. Suzuki, M. Hirata, IEEE J. Solid-State Circuits SC-14(6), 1066 (1979).

    Article  Google Scholar 

  41. T. Furuyama et al., “A New Sense Amplifier Technique for VLSI Dynamic RAM’s”, IEDM Ext. Abst., pp. 44–47, Dec. 1981.

    Google Scholar 

  42. L.G. Heller et al., IEEE J. Solid-State Circuits SC-11(5), 596 (1976).

    Article  Google Scholar 

  43. L.G. Heller, “Cross-Coupled Charge-Transfer Sense Amplifier”, ISSCC Dig. Tech. Papers, pp. 20–21, Feb. 1979.

    Google Scholar 

  44. M. Aoki et al., IEEE J. Solid-State Circuits 24(4), pp. 889–894, Aug. 1989.

    Article  Google Scholar 

  45. M. Aoki et al., Trans. IEICE, J73-C-II(5), 310 (1990).

    Google Scholar 

  46. M. Aoki et al., “A 1.5 V DRAM for Battery-Based Applications”, ISSCC Dig. Tech. Papers, pp. 238–239, Feb. 1989.

    Google Scholar 

  47. T. Nakano et al., “A Sub 100 ns 256 Kb DRAM”, ISSCC Dig. Tech. Papers, pp. 224–225, Feb. 1983.

    Google Scholar 

  48. S.S. Eaton et al., “A Sub 100 ns 64 K Dynamic RAM using Redundancy Techniques”, ISSCC Dig.Tech. Papers, pp. 84–85, Feb. 1981.

    Google Scholar 

  49. H. Kawamoto et al., “A 288 Kb CMOS Pseudo SRAM”, ISSCC Dig. Tech. Papers, pp. 276–277, Feb.1984.

    Google Scholar 

  50. R.I. Kung et al., “A Sub 100 ns 256 K DRAM in CMOS III Technology”, ISSCC Dig. Tech. Papers, pp. 278–279, Feb. 1984.

    Google Scholar 

  51. S. Suzuki et al., IEEE J. Solid-State Circuits SC-19(5), pp. 624–627, Oct. 1984.

    Article  Google Scholar 

  52. S. Saito et al., IEEE J. Solid-State Circuits, SC-20(5), 903 (1985).

    Article  Google Scholar 

  53. J.Y. Chan et al., IEEE J. Solid-State Corcuits SC-15(5), pp. 839–846, 1980.

    Article  Google Scholar 

  54. Y. Takemae et al., “A 1 Mb DRAM with 3-Dimensional Stacked Capacitor Cells”, ISSCC Dig. Tech. Papers, pp. 250–251, Feb. 1985.

    Google Scholar 

  55. N.C.C. Lu et al., IEEE J. Solid-State Circuits SC-20(6), pp. 1272–1276, 1985.

    Article  Google Scholar 

  56. A. Koike, Key issues in manufacturing of Giga era (VLSI Technology Workshop Digest 1996).

    Google Scholar 

  57. T. Hamamoto et al., “Well Concentration: A Novel Scaling Limitation Factor Derived from DRAM Retention Time and Its Modeling”, IEDM Ext. Abst., pp. 915–918, Dec. 1995.

    Google Scholar 

  58. M. Kojima et al., “Optimization of Giga-bit DRAM Cell Transistors by Channel and Drain Engineering”, SSD M Ext. Abst., pp. 36–37, Hiroshima, 1998.

    Google Scholar 

  59. H. Suzuki et al., “Trap Assisted Leakage Mechanism of ‘worst’ Junction in Giga-bit DRAM Using Negative Word-Line Voltage”, SSD M Ext. Abst., pp. 32–33, Hiroshima, 1998.

    Google Scholar 

  60. W.R. McKee et al., “Cosmic Ray Neutron Induced Upsets as a Major Contributor to the Soft Error Rate of Current and Future Generation DRAMs”, Int. Rel. Phys. Symp., pp. 1–6, April 1996.

    Google Scholar 

  61. S. Satoh et al., “Scaling Law for Secondary Cosmic-Ray Neutron-Induced Soft Errors in DRAMs”, SSD M Ext. Abst., pp. 40–41, Hiroshima, 1998.

    Google Scholar 

  62. A. Eto et al., “Impact of Neutron Flux on Soft Errors in MOS Memories”, IEDM Ext. Abst., pp. 367–370, Dec. 1998.

    Google Scholar 

  63. G. Bonner et al., “A Fully Planarized 0.25 mm CMOS Technology for 256 Mbit DRAM and Beyond”, Dig. Tech. Papers, 1995. symp. VLSI Technology, pp. 15, 1995.

    Google Scholar 

  64. K. Itoh et al., “VLSI Memory Technology: Current Status and Future Trends”, ESSCIRC’99 Dig. Tech. Papers, pp. 3–10, Sept. 1999.

    Google Scholar 

  65. Y. Ohji et al., “Reliability of Nano-Meter Thick Multi-Layer Dielectric Films on poly-Crystalline Silicon”, Tech. Dig. of International Reliability Physics symposium, p. 55, 1987.

    Google Scholar 

  66. T. Kisu et al., “A Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node in STC DRAM Cell”, Ext. Abstract, 20th Conf. On Solid State Devices and Materials, p. 581, 1988.

    Google Scholar 

  67. I. Asano et al., “1.5 nm Equivalent Thickness Ta2O5 High-k Dielectric with Rugged Si Suitable for Mass Production of High Density DRAMs”, IEDM Tech. Dig., p. 755, 1998.

    Google Scholar 

  68. H. Shinriki et al., IEEE Trans. Electron Devices, ED-37, 1939 (1990).

    Article  CAS  Google Scholar 

  69. H. Watanabe et al., “A New Cylindrical Capacitor using Hemisoherical Grained Si (HSG-Si) for 256 Mb DRAMs”, IEDM Tech. Dig., p. 259, 1992.

    Google Scholar 

  70. K. Ono et al., “(Ba, Sr)TiO3 Capacitor Technology for Gbit-Scale DRAMs”, IEDM Tech. Dig., p. 803, 1998.

    Google Scholar 

  71. K. Sunouchi et al., “Process Integration for 64 M DRAM using an Asymmetrical Stacked Trench Capacitor (AST) Cell”, IEDM Tech. Dig., p. 647, 1990.

    Google Scholar 

  72. H. Ishiuchi et al., “Embedded DRAM Technologies”, 1995 Symp. VLSI Technology, p. 33, 1997.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Central Research Laboratory, Hitachi Ltd., 1-280, Higashi-Koigakubo, Kokubunji-shi, Tokyo, 185-8601, Japan

    Dr. Kiyoo Itoh

Authors
  1. Dr. Kiyoo Itoh
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2001 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Itoh, K. (2001). High Signal-to-Noise Ratio DRAM Design and Technology. In: VLSI Memory Chip Design. Springer Series in Advanced Microelectronics, vol 5. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-04478-0_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-662-04478-0_4

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-08736-3

  • Online ISBN: 978-3-662-04478-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation