Propositional Temporal Logics

Abstract

All verification approaches presented in Chapter 3 are based on finite state machine theory. As the single available proof goal is FSM equivalence, we can verify only that two sequential circuits have the same behavior.¹ This simple equivalence check is sufficient to verify circuit optimizations where a modified circuit version still must be behaviorally equivalent to the original one. It is however not possible to specify and to verify more abstract circuit properties. This comprises all forms of partial specifications like safety, liveness and fairness properties.