Area and Delay Penalties in Restructurable Wafer-Scale Arrays

  • Jonathan W. Greene
  • Abbas EI Gamal


The penalties for restructuring wafer-scale arrays for yield enhancement are assessed. Each element of the fabricated array is assumed to be defective with independent probability p. A fixed fraction R of the elements are to be connected into a prespecified defect-free configuration by means of switched interconnections. The area penalty is determined by the required number of tracks per wiring channel t. Propagation delay is determined by the required maximum connection length d. It is shown that: Connection of RN fixed I/O ports to distinct nondefective elements from an N-element linear array requires d, t =θ(logN); Connection of RN pairs of elements from two N-element linear arrays requires only constant d and t; Connection of a chain of RN 2 elements from an N×N array also requires only constant d and t; Connection of a \(\sqrt R N \times \sqrt R N\) lattice from an N×N array requires \(d = \Omega (\sqrt {\log N} )\). Constant t suffices to connect a lattice if d=θ(logN). Algorithms are presented that connect any fraction R < l-p of the elements with probability approaching one as N increases. It appears that these results hold even under actual defect distributions.


Active Element Linear Array Occupied Site Source Vertex Connection Distance 
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Copyright information

© Computer Science Press, Inc. 1983

Authors and Affiliations

  • Jonathan W. Greene
    • 1
  • Abbas EI Gamal
    • 1
  1. 1.Information Systems LabStanford UniversityUSA

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