Zusammenfassung
Zur Erhöhung der Zuverlässigkeit eines Mikroprozessorsystems gibt es prinzipiell zwei Möglichkeiten:
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Fehler-intoleronz („foult-intolerance“, „fault-ovoidonce“): Unter diesem Begriff versteht man die Eliminierung der Fehlerursachen vor dem Einsatz des Systems. Dazu zählt z. B. die Auswahl besonders zuverlässiger Bauelemente, die unter Streß ausgetestet worden sind, sorgfältige Aufbau- und Abschirmtechniken und natürlich intensive Testverfahren — vor, während und nach dem Zusammenbau des Systems.
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Literatur
M. Dal Cin Fehl er tolerante Systeme Teubner Studienbücher Bd 50, Teubner Verlag Stuttgart 1979
E Moehle Fehl er tolerante Rechnerstrukturen Arbeitsbericht Bd 10, Nr. 4, 1977, Universität Erlangen Nürnberg
W. C. Carter, W. G. Bouricius A Survey of Foult-Tolerant Computer Architecture and ist Evaluation Computer, Vol 4, No. 1, 1971, pp. 9–16
F. P. Mothur Trends in Fault-Tolerant Computer Architecture Int. Workshop on Computer Architecture, Grenoble, 1973, pp. 1–44
A. Avizienis Architecture of Fault-Tolerant Computing Systems 1975 Int. Symposium of FouIt-Toleront Computing, pp. 3–16
A. Avizienis Fault-Tolerant Systems IEEE Trans on Com. C-25, No. 12, 1976, pp. 1304–1311
A. Avizienis Fault-Tolerant Computing-Progress, Problems, and Prospects 1977 IFIP Congress Proceedings, pp. 405–420
D. R. Bollard Designing Foil-Save Microprocessor Systems Electronics, Jon 4, 1979, pp. 139–143
B. Courtois Some Results About the Efficiency of Simple Mechanisms for the Detection of Microcomputer Malfunctions 1979 Int. Symposium of Fault Tolerant Computing, pp. 71–74
F. Ruf Aspekte bei der Zuverlässigkeit integrierter Schaltungen Elektronik 1980, Heft 23, S. 43–47
G. Saucier Design Methodology of High Safety Systems on Microprocessors Euromicro Symposium 1978, pp. 160–166
J. C. Geffroy, M. Diaz Unified Approach to the Study of Self-Checking Systems Digital Processes, 3, 1977, pp. 289–306
J. F. Wakerly Partially Self-Checking Circuits and their Use in Performing Logical Operations IEEE Trans on Comp C-23, No. 7, 1974, pp. 658–666
W. C. Carter, K. A. Duke, D. C. Jessep A Simple Self-Testing Decoder Checking Circuit IEEE Trans on Comp. Vol. C-20, 1971, pp. 1413–1414
Ro E. Lyons, W. Vanderkulk The Use of Triple Modular Redundancy to Improve Computer Reliability IBM Journal of Res. and Develop. Vol. 6, No. 2, 1962
D. P. Sieworek Reliability Modeling of Compensating Module Failures in Majority Voted Redundancy IEEE Trans on Comp. Vol. C-24, No. 5, 1975
W. G. Broucious, W. C. Carter, P. Ro Schneider Reliability Modeling Techniques for Self-Repairing Computer Systems Proc. of 24th Not. Conf. of ACM, 1969, pp. 295–383
F. P. Mothur On Reliability Modeling an Analysis of Ultrarelioble Fault-Tolerant Digital Systems IEEE Trans on Comp., Nov. 1971, pp. 1376–1381
C. A. Papen fuss The Availability, Reliability and Maintainability of Redundant Systems General Electric Company, Sept. 1974
H. Y. H. Chuong, S. Dos An Approach to the Design of Highly Reliable and Foil-Sofe Digital Systems Notional Computer Conference 1974, pp. 637–642
J.F. Wokerly Microcomputer Reliability Improvement Using Triple-Modular Redundancy Proc. of the IEEE, Vol. 64, No. 6, 1976, pp. 889–895
B. R. Borgerson, R. F. Freitos A Reliability Model for Graceful Degradation and Standby Sparing Systems IEEE Trans on Comp. Vol. C-24, 1975, pp. 517–525
J. Goldberg, K. W. Levitt, J. H. Wensley An Organization for o Highly Survivoble Memory IEEE Trans on Comp. Vol. C-23, 1974, pp. 693–705
F. P. Mothur, A. Avizienis Reliability Analysis for a Hybrid-Redundant Digital System: Generalized Triple Modular Redundancy with Self Repair AFIPS Conf. Proc. Vol. 36, 1970, pp. 375–383
W. C. Carter et al A Theory of Design of Fault-Tolerant Computer Using Standby Sparing 1971 Int. Symposium of Fou It-Tolerant Computing, pp. 83–86
D. P. Sieworek, E. J. Mc Clusky Switch Complexity in Systems with Hybrid Redundancy IEEE Trans on Comp Vol. C-22, No. 3, 1973, pp. 276–282
A. D. Ingle, D. P. Sieworek A Reliability Model for Various Switch Designs in Hybrid Redundancy IEEE Trans on Comp, Vol. C-25, No. 2, 1976, pp. 115–133
A. Avizienis et al The STAR (Self-Testing-and-Repair) Computer: An Investigation of the Theory and Practice on Fault-Tolerant Computer Design IEEE Trans on Comp. Vol. C-20, No. 11, 1971, pp. 1312–1321
C. V. Ramomoorthy, Y. Han Reliability Analysis of Systems with Concurrent Error Detection IEEE Trans on Comp. Vol. C-24, No. 9, 1975, pp. 868–878
R. E. Kuehn Computer Redundancy: Design, Performance, and Future IEEE Trans on Rel. Vol. R-18, No. 1, 1969, pp. 3–11
R. Hedtke Fehlertolerante Halbleiterspeicher D 17 Darmstädter Dissertation, 1979
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Hedtke, R. (1984). Redundanztechniken. In: Mikroprozessorsysteme. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-93257-1_7
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