A Configurable Micro Array Computer for Signal and Image Processing

Abstract

The increasing use of industrial robots will create a demand for inexpensive but powerful vision systems. Only multi microprocessor systems offer the opportunity of combining cost-effectiveness (through the use of VLSI components) with high performance (through parallel processing). The problem, however, is the large diversity of the image understanding procedures, ranging from array processing of gray scale matrices to sophisticated classification or decision making programs. Whereas a pipeline architecture is most adequate for vector processing (e.g. FFT), segmentation and feature extraction algorithms usually lend themselves toward parallel processing performed in a lock-step fashion by a number of general-purpose processing modules, and classification and image understanding algorithms eventually call for a machine exhibiting high-performance of scalar floating point operations. The answer to these contradicting requirements is a configurable architecture. Such an architectural design is outlined in the paper. Special considerations are given to the problem of programmabi1ity and system software that shall enable the user to program an application in an appropriate, high-level, parallel processing language, independent of the actual configuration of the system.