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VLSI Array Architecture for Picture Processing

  • P. S. Liu
  • T. Y. Young
Part of the Springer Series in Information Sciences book series (SSINF, volume 6)

Abstract

Many operations in picture or image processing are performed repeatedly over a large number of pixels of an image, and computation time can be reduced significantly by parallel processing. With rapid progress in VLSI technology, it will be feasible in the near future to design and fabricate VLSI array chips for certain special image processing operations. These special purpose chips can be connected to the host computer system through the system bus.

Keywords

Matrix Multiplication Computer Architecture Systolic Array VLSI Architecture Band Matrix 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1982

Authors and Affiliations

  • P. S. Liu
    • 1
  • T. Y. Young
    • 1
  1. 1.Department of Electrical EngineeringUniversity of MiamiCoral GablesUSA

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