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High-level Petri Nets pp 576–595Cite as

Specification and Properties of a Cache Coherence Protocol Model

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Abstract

This paper describes a cache coherence protocol for an architecture composed of several processors, each with their own local cache, connected via a switching structure to a shared memory itself split into several modules managed by independent controllers. The protocol prevents processors from simultaneously modifying their respective copies and always provides a processor requiring a copy of a memory location with the most up-to-date version. A top down description and modeling of the protocol is given using Predicate/Transition nets. This modeling allows to formally describe the complex synchronizations of this protocol. Then invariants are directly obtained without unfolding the Predicate/Transition net. They are the basis for studying behavioral properties.

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Authors
  1. C. Girault
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  2. C. Chatelain
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  3. S. Haddad
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Editor information

Editors and Affiliations

  1. Computer Science Department, Aarhus University, Ny Munkegade, Bldg. 540, DK-8000, Aarhus C, Denmark

    Kurt Jensen

  2. Institute of Applied Mathematics and Computer Science, University of Leiden, Niels-Bohr-Weg 1, 2333, CA, Leiden, The Netherlands

    Grzegorz Rozenberg

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© 1991 Springer-Verlag Berlin Heidelberg

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Girault, C., Chatelain, C., Haddad, S. (1991). Specification and Properties of a Cache Coherence Protocol Model. In: Jensen, K., Rozenberg, G. (eds) High-level Petri Nets. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-84524-6_22

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  • DOI: https://doi.org/10.1007/978-3-642-84524-6_22

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-54125-7

  • Online ISBN: 978-3-642-84524-6

  • eBook Packages: Springer Book Archive

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