Skip to main content

Parallel and Supercomputer Architecture in Japan

  • Chapter
  • 67 Accesses

Part of the book series: Lecture Notes in Engineering ((LNENG,volume 69))

Abstract

Parallel processing is the technology for speedup of computers. There are several ways of realizing it. According to the well-known Flynn classification of von Neumann machines into SISD, SIMD, MISD and MIMD types, parallel processing is commercially due to the SIMD and MIMD types. In this seminar, we focus on supercomputers (primarily in Japan) based on pipelining. Currently, Japanese supercomputers have a tendency to challenge to realize the peak performance using only multiple-parallel pipelining. We describe Japanese supercomputers with their advantages and disadvantages compared with the Cray series. In view of supercomputer architecture, though Japanese systems have features of speedup in linear data structures, there may be a few problems in their reliability, flexibility, and availability. In addition to improvement of throughput, these problems may be solved by means of multiprocessor system development. However, we are going to mention the other possibility of solving these problems in Japanese supercomputers by using an MISD concept.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. L. Uhr, “Multi-computer architectures for artificial intelligence,” Wiley Interscience, 1987.

    Google Scholar 

  2. K. Hwang, “Multiprocessor supercomputers for scientific/engineering applications,” Computer, vol. 18, no. 6, pp. 57–73, June 1985.

    Article  Google Scholar 

  3. V. M. Milutinovic’, “Computer Architecture,” North-Holland, 1982.

    Google Scholar 

  4. K. Hwang and D. Degroot, “Parallel Processing for super-computers and artificial intelligence,” Mc Graw-Hi11,1989.

    Google Scholar 

  5. T. Watanabe, T. Furukatsu, R. Kondo, T. Kawamura and Y. Izutani, “The supercomputer SX system: An overview,” Proc ICS’87 supercomputing vol. 1, pp 51–56, 1987.

    Google Scholar 

  6. T. Nakamura, Y. Takai and T. L. Kunii, “Pipelined supercomputing with list-structured data,” Proc ICS’87 supercomputing vol. 1, pp 410–415, 1987.

    Google Scholar 

  7. T. L. Kunii, “Application development systems,” Springer-Verlag, 1986.

    Google Scholar 

  8. P. C. Patton, “Multiprocessors: Architecture and applications,” Computer, vol. 18, no. 6, pp. 29–40, June 1985.

    Article  Google Scholar 

  9. J. Backus, “Can programming be liberated from the von Neumann style? A functional style and its algebra of programs,” Comm. ACM, vol. 21, pp. 613–641, Aug. 1978.

    Article  MATH  MathSciNet  Google Scholar 

  10. T. Nakamura, “Software of the brain structured computer,” Proc. of The IEEE Eighth International Computer Software & Applications Conference, pp. 408–414, Nov. 1984.

    Google Scholar 

  11. L. A. Zadeh, “Coping with the imprecision of the real world,” Comm. ACM, vol. 27, pp. 304–311, Apr. 1984.

    Article  MathSciNet  Google Scholar 

  12. T. Nakamura, K. Sakai and Y. Mishina, “Function-level computing on the brain structured computer,” Proc. of the IEEE Ninth International Computer Software & applications Conference, pp. 90–96, Oct. 1985.

    Google Scholar 

  13. M. Amamiya, M Takesue, R. Hasegawa and H. Mikami, “Implementation and evaluation of a list-processing-oriented data flow machine,” The 13th Annual International Symposium on Computer Architecture Conference Proc., pp. 10–19, June 1986.

    Google Scholar 

  14. J. Backus, “Function-level computing,” IEEE Spectrum, vol. 19, no. 8, pp. 22–27, Aug. 1982.

    Google Scholar 

  15. A. Iizawa and T. L. Kunii, “Graph-based design specification of parallel computation,” Lecture Notes in Computer Science 163, VLSI engineering, Springer-Verlag, 1984.

    Google Scholar 

  16. H. Kobayashi, N. Endo, T. Nakamura and Y. Shigei, “Performance evaluation of a general purpose pipeline system,” Trans. IECE Japan, vol. J68-D, no. 10, pp. 1744–1752, Oct. 1985.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1991 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Nakamura, T. (1991). Parallel and Supercomputer Architecture in Japan. In: Murthy, T.K.S., Brebbia, C.A. (eds) Advances in Computer Technology and Applications in Japan. Lecture Notes in Engineering, vol 69. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-84514-7_2

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-84514-7_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-54072-4

  • Online ISBN: 978-3-642-84514-7

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics