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Pyramid Algorithms on Processor Arrays

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Pyramidal Systems for Computer Vision

Part of the book series: NATO ASI Series ((NATO ASI F,volume 25))

Abstract

A class of adaptive grid size algorithms, called pyramid algorithms, have received much attention in recent years for computer vision applications. Special hardware architectures which are optimal for grid resolution transformations have been proposed to implement these algorithms. In this chapter analysis techniques are described which measure the effectiveness of different architectures. A comparison is made between the more conventional planar or flat architecture and the optimal pyramid architecture. It is shown that in many cases the additional hardware of the pyramid scheme offers little improvement in performance.

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References

  1. K. E. Batcher, “Design of a Massively Parallel Processor” IEEE Transactions on Computers C-29(9) pp. 836–840 (September 1981).

    Article  Google Scholar 

  2. A. P. Reeves, “On Efficient Global Information Extraction Methods For Parallel Processors,” Computer Graphics and Image Processing 14 pp. 159–169 (1980).

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  3. A. P. Reeves, “Parallel Pascal: An Extended Pascal for Parallel Computers,” Journal of Parallel and Distributed Computing 1 pp. 64–80 (1984).

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  4. A. P. Reeves, “The Anatomy of VLSI Binary Array Processors,” in Languages and Architectures for Image Processing, ed. M. J. B. Duff and S. Levialdi, Academic Press (1981).

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  5. R. W. Gostick, “Software and Algorithms for the Distributed-Array Processor,” ICL Technical Journal, pp. 116–135 (May 1979).

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  6. NCR Corporation, Geometric Arithmetic Parallel Processor, NCR, Dayton, Ohio (1984).

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  7. A. P. Reeves and T. H. Moura, “Data Manipulations on the Massively Parallel Processor,” Proceedings of the Nineteenth Hawaii International Conference on System Sciences, pp. 222–229 (January, 1986 ).

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  8. P. J. Burt, “Fast Filter Transforms for Image Processing,” Computer Graphics and Image Processing 16 pp. 20–51 (1981).

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© 1986 Springer-Verlag Berlin Heidelberg

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Reeves, A.P. (1986). Pyramid Algorithms on Processor Arrays. In: Cantoni, V., Levialdi, S. (eds) Pyramidal Systems for Computer Vision. NATO ASI Series, vol 25. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-82940-6_13

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  • DOI: https://doi.org/10.1007/978-3-642-82940-6_13

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-82942-0

  • Online ISBN: 978-3-642-82940-6

  • eBook Packages: Springer Book Archive

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