Abstract
Through the use of massive parallelism, Intelligent Memory offers many solutions to software problems. However bus interaction and contention remains a major problem. This paper addresses these problems and highlights possible solutions.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
G. Farber, A Decentralised Fair Bus Arbiter, Euromicro V7 N1 1981
J. Nadir & B. McCormick, Bus Arbiter Streamlines Multi-Processor Design, Computer Design V19 N6 1980
E. Petriu, N-Channel Asynchronous Arbiters Resolves Resource Allocation Conflicts, Computer Design V19 N8 1972
A.B. Kovaleski, High Speed Bus Arbiter for Multi-Processors, I.E.E.E. Proc. V130 N2 1983
W.W. Plummer, Asynchronous Arbiters, I.E.E.E. Transactions on Computers V21 N1 1972
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1986 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Roach, A.K., Quick, G.E. (1986). Bus Arbitration Concepts for the Fifth Generation Advance. In: Sood, A.K., Qureshi, A.H. (eds) Database Machines. NATO ASI Series, vol 24. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-82937-6_18
Download citation
DOI: https://doi.org/10.1007/978-3-642-82937-6_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-82939-0
Online ISBN: 978-3-642-82937-6
eBook Packages: Springer Book Archive