Architectures of SIMD Cellular Logic Image Processing Arrays

Abstract

The use of parallelism in the design of computer architectures specialised for image processing is now recognised as a necessity, especially as interest grows in the potential applications of real-time image analysis. A conventional (von Neumann) serial processor is clearly unable to achieve processing rates which would keep up with the data flow from standard television image sequences. Suppose that it is required to perform a simple, 3 × 3 local neighbourhood operation on a new 512 × 512 pixel image every one twenty-fifty of a second. This operation would involve, at every pixel, fetching nine pixel values and performing at least eight additions (although there would most likely be multiplications involved as well), concluding with a store operation. Over and above this activity in the arithmetic logic unit, input and output operations would also be required. Thus in one second, the minimum number of processor operations would be 25 × 512 × 512 × (8 additions + 9 memory accesses), i.e. more than 100 million operations each second. Improvements in semiconductor technology can be expected to go some of the way towards enhancing computer performance towards rates in this region, but the bulk of the gain must still be found elsewhere and, specifically, in improved architectures.