Abstract
Arrays with a large number of bit-serial processors have long been suggested for high speed image processing. The set of necessary algorithms and operations seem to require a number of new features in the architecture. Of special importance are the so-called distributed processor topology for fast neighborhood access, and index arithmetic for table-look up. From a hard-ware point of view, however, the added complexity of the processors is also a threat to the bit-serial approach.
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© 1985 Springer-Verlag Berlin Heidelberg
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Danielsson, PE. (1985). Algorithm-Driven Architecture for Parallel Image Processing. In: Freeman, H., Pieroni, G.G. (eds) Computer Architectures for Spatially Distributed Data. NATO ASI Series, vol 18. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-82150-9_1
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DOI: https://doi.org/10.1007/978-3-642-82150-9_1
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