Abstract
Since microprocessors are used in many areas of real-time control, the use of formal methods provides an alternative approach for achieving high reliability. In this paper, a methodology based on a hierarchical model of interpreters is presented for formalizing RISCs in general. The abstraction levels used by a designer in the implementation of RISCs, namely the instruction set level, the pipeline stage level, the phase level and the hardware implementation, are mirrored by this hierarchical model. Hence the informal specifications given by the user, at each level of abstraction, can be easily converted into a formal specification, in higher order logic. Such a model is of great use in formal verification and also synthesis using transformational reasoning.
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Tahar, S., Kumar, R. (1993). A Formalization of a Hierarchical Model for RISC Processors. In: Spies, P.P. (eds) Europäischer Informatik Kongreß Architektur von Rechensystemen Euro-ARCH ’93. Informatik aktuell. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-78565-8_47
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DOI: https://doi.org/10.1007/978-3-642-78565-8_47
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